US 2006/0040448 A1 · METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING IMPROVED HOT CARRIER IMMUNITY ABILITY

Abstract

The present invention discloses a method for fabricating a semiconductor device. A substrate is provided. At least one first and second gate structure, having sidewalls, are included on a surface of the substrate. A first ion implantation process is performed to form a shallow-junction doping region of a first conductive type in the substrate next to each of the sidewalls of the first gate structure, followed by the formation of offset spacers on each of the sidewalls of the first and second gate structure. A second ion implantation process is performed to form a shallow-junction doping region of a second conductive type in the substrate next to the offset spacer on each of the sidewalls of the second gate structure.

Claims28

Dependent claims

A method for fabricating a semiconductor device comprising:

providing a substrate, at least one first gate structure and at least one second gate structure being included on a surface of the substrate, both the first gate structure and the second gate structure having sidewalls;
performing a first ion implantation process to form a shallow-junction doping region of a first conductive type in the substrate next to each of the sidewalls of the first gate structure;
forming offset spaces on each of the sidewalls of the first gate structure and the second gate structure;
and
performing a second ion implantation process to form a shallow-junction doping region of a second conductive type in the substrate next to the offset spacer on each of the sidewalls of the second gate structure.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

10/711,038Filed 19 Aug 2004

Published

23 Feb 2006

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/0184
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their gate sidewall spacers
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…

Method for fabricating a semiconductor device having improved hot carrier immunity ability

Life of this patent

Method for fabricating a semiconductor device having improved hot carrier immunity ability

Life of this patent

Abstract

Claims28