NAND memory arrays and methods

A method of forming a NAND memory array, comprising:

• forming a first dielectric layer on a semiconductor substrate;
• forming a hard mask layer on the first dielectric layer;
• removing a portion of the hard mask layer and the first dielectric layer to expose a portion of the substrate adjacent a remaining portion of the first dielectric layer;
• forming a second dielectric layer on the exposed portion of the substrate, wherein the second dielectric layer is thinner than the first dielectric layer;
• removing the hard mask layer from the remaining portion of the first dielectric layer;
• forming a first gate stack on the first dielectric layer to form a drain select gate;
• and
• forming a string of second gate stacks on the second dielectric layer to form a NAND string of floating-gate memory cells, wherein a first memory cell of the NAND string is adjacent the drain select gate.

A method of forming a NAND memory array, comprising:

• forming a first dielectric layer on a semiconductor substrate;
• forming a hard mask layer on the first dielectric layer;
• patterning the hard mask layer for removing a portion of the hard mask layer and the first dielectric layer to expose a portion of the substrate adjacent a remaining portion of the first dielectric layer;
• removing the portion of the hard mask layer and the first dielectric layer to expose the portion of the substrate;
• forming a second dielectric layer on the exposed portion of the substrate, wherein the second dielectric layer is thinner than the first dielectric layer;
• removing the hard mask layer from the remaining portion of the first dielectric layer;
• forming a first conductive layer on the first and second dielectric layers;
• forming a third dielectric layer of the first conductive layer;
• forming a second conductive layer on the third dielectric layer;
• removing portions of the second conductive layer, the third dielectric layer, and the first conductive layer to expose portions of the first and second dielectric layers and to form a first gate stack on the first dielectric layer, a second gate stack on the second dielectric layer, and a string of third gate stacks on the second dielectric layer between the first and second gate stacks;
• wherein the first dielectric layer with the first gate stack formed thereon forms a drain select gate, the second dielectric layer with the second gate stack formed thereon forms a source select gate, and the second dielectric layer with the string of third gate stacks formed thereon forms a NAND string of memory cells between the drain and source select gates.

A method of forming a NAND memory array, comprising:

• forming a first oxide layer on a semiconductor substrate;
• forming a nitride layer on the first oxide layer;
• patterning the nitride layer for removing a portion of the nitride layer and the first oxide layer to expose a portion of the substrate adjacent a remaining portion of the first oxide layer;
• removing the portion of the nitride layer and the first oxide layer to expose the portion of the substrate;
• forming a second oxide layer on the exposed portion of the substrate, wherein the second oxide layer is thinner than the first oxide layer;
• nitridizing the second oxide layer;
• removing the nitride layer from the remaining portion of the first oxide layer;
• forming a polysilicon layer on the first and second oxide layers;
• forming a dielectric layer of the polysilicon layer;
• forming a conductive layer on the dielectric layer;
• removing portions of the conductive layer, the dielectric layer, and the polysilicon layer to expose portions of the first and second oxide layers and to form a first gate stack on the first oxide layer, a second gate stack on the second oxide layer, and a string of third gate stacks on the second oxide layer between the first and second gate stacks;
• wherein the first oxide layer with the first gate stack formed thereon forms a drain select gate, the second oxide layer with the second gate stack formed thereon forms a source select gate, and the second oxide layer with the string of third gate stacks formed thereon forms a NAND string of memory cells between the drain and source select gates.

A NAND memory array comprising:

• a plurality of rows of memory cells;
• and
• a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a drain select gate of the respective column;
• wherein each of the drain select gates comprises a first dielectric layer formed on a semiconductor substrate of the memory array and a control gate formed on the first dielectric layer;
• and
• wherein each of the memory cells of each of the NAND strings comprises a second dielectric layer formed on the substrate adjacent the first dielectric layer, a floating gate formed on the second dielectric layer, a third dielectric layer formed on the floating gate, and a control gate formed on the third dielectric layer, wherein the first dielectric layer is thicker than the second dielectric layer.

A NAND memory array comprising:

• a plurality of rows of memory cells;
• and
• a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a drain select gate of the respective column;
• wherein each of the drain select gates comprises a first dielectric layer formed on a semiconductor substrate of the memory array and a first conductive layer formed on the first dielectric layer;
• wherein each of the memory cells of each of the NAND strings comprises a second dielectric layer formed on the substrate adjacent the first dielectric layer and the first conductive layer formed on the second dielectric layer, wherein the first dielectric layer is thicker than the second dielectric layer;
• and
• wherein each of the drain select gates and each of the memory cells of each of the NAND strings further comprises a third dielectric layer formed on the first conductive layer and a second conductive layer formed on the third dielectric layer.

A NAND memory array comprising:

• a plurality of rows of memory cells;
• and
• a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a drain select gate of the respective column;
• wherein each of the drain select gates comprises a first oxide layer formed on a semiconductor substrate of the memory array and a polysilicon layer formed on the oxide layer;
• wherein each of the memory cells of each of the NAND strings comprises a nitride-containing second oxide layer formed on the substrate adjacent the first oxide layer and the polysilicon layer formed on the nitride-containing second oxide layer, wherein the first oxide layer is thicker than the nitride-containing second oxide layer;
• and
• wherein each of the drain select gates and each of the memory cells of each of the NAND strings further comprises a dielectric layer formed on the polysilicon layer, and a conductive layer formed on the dielectric layer.

A memory device comprising:

• a memory array comprising:
• a plurality of rows of memory cells, each row connected to a word line;
• and
• a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a drain select gate of the respective column;
• wherein each of the drain select gates comprises a first dielectric layer formed on a semiconductor substrate of the memory array and a control gate formed on the first dielectric layer;
• and
• wherein each of the memory cells of each of the NAND strings comprises a second dielectric layer formed on the substrate adjacent the first dielectric layer, a floating gate formed on the second dielectric layer, a third dielectric layer formed on the floating gate, and a word line formed on the third dielectric layer, wherein the first dielectric layer is thicker than the second dielectric layer;
• column access circuitry connected to the bit lines;
• and
• row access circuitry connected to the word lines.

A memory device comprising:

• a memory array comprising:
• a plurality of rows of memory cells, each row connected to a word line;
• and
• a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a drain select gate of the respective column;
• wherein each of the drain select gates comprises a first dielectric layer formed on a semiconductor substrate of the memory array and a first conductive layer formed on the first dielectric layer;
• wherein each of the memory cells of each of the NAND strings comprises a second dielectric layer formed on the substrate adjacent the first dielectric layer and the first conductive layer formed on the second dielectric layer, wherein the first dielectric layer is thicker than the second dielectric layer;
• and
• wherein each of the drain select gates and each of the memory cells of each of the NAND strings further comprises a third dielectric layer formed on the first conductive layer, and a second conductive layer formed on the third dielectric layer;
• column access circuitry connected to the bit lines;
• and
• row access circuitry connected to the word lines.