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US 2006/0040438 A1Published application
Method for improving the thermal stability of silicide
OwnerJiong-Ping Lu, Jiejie Xuinventors
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Abstract
An embodiment of the invention is a method of making a transistor by performing an ion implant on a gate electrode layer 110. The method may include forming an interface layer 200 over the semiconductor substrate 20 and performing an anneal to create a silicide 190 on the top surface of the gate electrode 110.
Claims28
A method for making a transistor, comprising:
- providing a semiconductor substrate;
- forming a gate dielectric layer over said semiconductor substrate;
- forming a gate electrode layer over said gate dielectric layer;
- and
- performing an ion implant on said gate electrode layer.
2 more elements
A method for forming a silicide on a gate of a transistor, comprising:
- providing a semiconductor substrate;
- forming a gate dielectric layer over said semiconductor substrate;
- forming a gate electrode layer over said gate dielectric layer, said gate electrode layer comprising polycrystalline silicon;
- performing an Ar+ion implant on said gate electrode layer;
- etching said gate electrode layer and said gate dielectric layer to form a gate stack having a gate electrode and a gate dielectric;
- forming extension sidewalls coupled to said gate stack;
- implanting extension regions within a top surface of said semiconductor substrate;
- forming source/drain sidewalls coupled to said extension sidewalls;
- implanting source/drain regions within a top surface of said semiconductor substrate;
- annealing said semiconductor substrate to recrystallize a surface region of said gate electrode modified by said Ar+ion implant;
- forming an interface layer over said semiconductor substrate, said interface layer including Ni;
- and
- performing a rapid thermal anneal to create a nickel silicide within said surface region of said gate electrode.
10 more elements
A method for forming a silicide on a gate of a transistor, comprising:
- providing a semiconductor substrate;
- forming a gate dielectric layer over said semiconductor substrate;
- forming a gate electrode layer over said gate dielectric layer;
- etching said gate electrode layer and said gate dielectric layer to form a gate stack having a gate electrode and a gate dielectric;
- forming extension sidewalls coupled to said gate stack;
- implanting extension regions within a top surface of said semiconductor substrate;
- forming source/drain sidewalls coupled to said extension sidewalls;
- implanting source/drain regions within a top surface of said semiconductor substrate;
- performing an Ar+ion implant;
- annealing said semiconductor substrate;
- forming an interface layer over said semiconductor substrate;
- and
- performing an anneal to create a silicide on a top surface of said gate electrode.
10 more elements
Dependencies are inferred from the claim text.