Graded semiconductor layer

A method of forming a semiconductor structure comprising:

• providing a wafer, the wafer includes a first semiconductor layer, wherein the first semiconductor layer includes silicon and germanium and wherein the first semiconductor layer includes a first portion having a first concentration of germanium and a second portion having a second concentration of germanium, wherein the first portion overlies the second portion, and wherein the first concentration is less than the second concentration;
• performing a condensation process on the first semiconductor layer to consume a portion of the first semiconductor layer and to form a material including silicon overlying a remaining portion of the first semiconductor layer;
• removing the material including silicon;
• forming a second semiconductor layer including silicon over the remaining portion after the removing the material including silicon.

A method of forming a semiconductor device comprising:

• providing a wafer having a semiconductor on insulator (SOI) configuration, the wafer including a first semiconductor layer over an insulator, the first semiconductor layer including germanium and silicon, the first semiconductor layer including a first portion of the first semiconductor layer overlying a second portion of the first semiconductor layer, wherein the first portion includes a first concentration of germanium and wherein the second portion includes a second concentration of germanium, further wherein the first concentration is less than the second concentration;
• and
• performing an oxidation process on the first semiconductor layer to consume a portion of the first semiconductor layer and to form an oxide on a remaining portion of the first semiconductor layer;
• removing the oxide;
• forming a second semiconductor layer including silicon over the remaining portion using the remaining portion as a template layer after the removing the oxide;
• forming a transistor including a channel region, at least a portion of the channel region is located in the second semiconductor layer.