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US 2006/0039487 A1Published application
Clocking architectures in high-speed signaling systems
AssigneeRambus Inc.
InventorScott Best
Life of this patent
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Abstract
Clocking systems and methods are provided below that accurately clock per-pin data transfers of input/output (IO) circuits of integrated circuit devices. These multiplexer-based clock selection systems use a dedicated multiplexer to receive clock signals from multiple mixer circuits and in turn to provide a selected reference clock signal for use by an interface circuit in transferring data to other integrated circuit devices. The timing of the selected reference clock signal is synchronized with the data signals to provide optimal sampling of the data signals. The multiplexer-based clock selection system is for use in memory interfaces of high-speed signaling systems for example.
Claims42
A circuit comprising:
- a plurality of mixer circuits, each mixer circuit of the plurality of mixer circuits to receive a first clock signal at an input and to output a reference clock signal having one of a plurality of phases;
- a multiplexer to receive the reference clock signal from each mixer circuit of the plurality of mixer circuits and to output a selected clock signal of the received reference clock signals;
- an interface circuit coupled to the multiplexer output, the interface circuit to transfer data in response to the selected clock signal;
- and
- a control circuit, coupled to the multiplexer, to select the selected clock signal in response to relative timing information of each of the reference clock signals and data signals.
2 more elements
A circuit comprising:
- a clock synthesis circuit to receive a system clock signal at an input and to output a plurality of reference signals;
- a plurality of mixer circuits, each mixer circuit of the plurality of mixer circuits to receive the plurality of reference signals and to output at least one reference clock signal having one of a plurality of phases;
- a multiplexer to receive the at least one reference clock signal from each mixer circuit of the plurality of mixer circuits and to output a selected clock signal of the received reference clock signals;
- an interface circuit having a clock input coupled to the multiplexer output, the interface circuit to transfer a data signal with a memory device under control of the selected reference clock signal;
- and
- at least one control circuit coupled to control the multiplexer and at least one mixer circuit of the plurality of mixer circuits, the control circuit controlling the multiplexer to select and output the selected clock signals in response to timing information of each of the reference clock signals relative to the data signals.
3 more elements
A system comprising:
- a plurality of mixer circuits each coupled to receive a first clock signal at an input and to output at least one reference clock signal having one of a plurality of phases;
- a plurality of multiplexers each coupled to receive the reference clock signals from each of the plurality of mixer circuits and each outputting a selected clock signal of the reference clock signals;
- a plurality of interface circuits each having a clock input coupled to an output of one of the plurality of multiplexers, the interface circuits each controlling data transfers over one of a plurality of signal lines under control of the selected clock signal;
- and
- at least one control circuit coupled to control the plurality of multiplexers to select and output the selected clock signal in response to relative timing information of the reference clock signals and data signals of the plurality of signal lines.
2 more elements
A method comprising:
- generating a plurality of clock signals, each clock signal of the plurality of clock signals having one of a plurality of phases;
- selecting one clock signal of the plurality of clock signals for output from each mixer of a plurality of mixers and, in response, outputting a reference clock signal from each mixer of the plurality of mixers;
- coupling the reference clock signal as an input to at least one multiplexer;
- coupling an output of the multiplexer to control data transfers via a pin and associated signal line of an interface circuit;
- selecting one of the reference clock signals for output from the multiplexer using timing information of all reference clock signals relative to data signals on the associated pin and signal line;
- and
- clocking the data transfers with the multiplexer output.
4 more elements
A circuit comprising:
- means for generating a plurality of clock signals each having one of a plurality of phases;
- means for selecting one of the clock signals for output from each of a plurality of mixers and in response outputting a reference clock signal from each mixer;
- means for coupling each reference clock signal as an input to at least one multiplexer;
- means for coupling an output of the multiplexer to control data transfers via a pin and associated signal line of an interface circuit;
- means for selecting one of the reference clock signals for output from the multiplexer using timing information of all reference clock signals relative to data signals on the associated pin and signal line;
- and
- means for clocking the data transfers with the multiplexer output.
4 more elements
A machine readable media including a description of a circuit, the circuit comprising:
- a plurality of mixer circuits each coupled to receive a first clock signal at an input and to output at least one reference clock signal having one of a plurality of phases;
- a multiplexer coupled to receive the reference clock signals from each of the plurality of mixer circuits and to output a selected clock signal of the reference clock signals;
- an interface circuit coupled to the multiplexer output and transferring data over a signal line under control of the selected clock signal;
- and
- a control circuit coupled to control the multiplexer to select and output the selected clock signal in response to relative timing information of each of the reference clock signals and data signals of the signal line.
2 more elements
Dependencies are inferred from the claim text.