High speed downlink packet access co-processor for upgrading the capabilities of an existing modem host

A high speed downlink packet access (HSDPA) co-processor for enhancing the capabilities of a modem host in a wireless transmit/receive unit (WTRU), the HSDPA co-processor comprising:

• (a) a receiver subsystem;
• (b) a shared memory arbiter (SMA) memory in communication with the receiver subsystem;
• (c) at least one interface for communicating with the modem host;
• and
• (d) a receiver subframer in communication with the SMA memory.

An integrated circuit (IC) for enhancing the capabilities of a modem host in a wireless transmit/receive unit (WTRU), the IC comprising:

• (a) a receiver subsystem;
• (b) a shared memory arbiter (SMA) memory in communication with the receiver subsystem;
• (c) at least one interface for communicating with the modem host;
• and
• (d) a receiver subframer in communication with the SMA memory.

A high speed downlink packet access (HSDPA) co-processor for enhancing the capabilities of a modem host in a wireless transmit/receive unit (WTRU), the HSDPA co-processor comprising:

• (a) a normalized least mean square (NLMS) chip level equalizer (CLE) receiver for receiving in-phase (I)/quadrature (Q) samples;
• (b) an HSDPA despreader in communication with an output of the NLMS CLE receiver;
• (c) a chip level equalizer post processor (CLEPP) in communication with the NLMS CLE receiver and the HSDPA despreader;
• (d) a high speed shared control channel (HS-SCCH) decoder in communication with the HSDPA despreader and the CLEPP;
• and
• (e) a channel quality indicator (CQI) estimator in communication with the HSDPA despreader for providing CQI information to the modem host.

A high speed downlink packet access (HSDPA) co-processor for enhancing the capabilities of a modem host in a wireless transmit/receive unit (WTRU), the HSDPA co-processor comprising:

• (a) a Rake receiver for receiving in-phase (I)/quadrature (Q) samples;
• (b) an HSDPA despreader in communication with an output of the Rake receiver;
• (c) a chip level equalizer post processor (CLEPP) in communication with the Rake receiver and the HSDPA despreader;
• (d) a high speed shared control channel (HS-SCCH) decoder in communication with the HSDPA despreader and the CLEPP;
• and
• (e) a channel quality indicator (CQI) estimator in communication with the HSDPA despreader for providing CQI information to the modem host.

An integrated circuit (IC) for enhancing the capabilities of a modem host in a wireless transmit/receive unit (WTRU), the IC comprising:

• (a) a normalized least mean square (NLMS) chip level equalizer (CLE) receiver for receiving in-phase (I)/quadrature (Q) samples;
• (b) a high speed downlink packet access (HSDPA) despreader in communication with an output of the NLMS CLE receiver;
• (c) a chip level equalizer post processor (CLEPP) in communication with the NLMS CLE receiver and the HSDPA despreader;
• (d) a high speed shared control channel (HS-SCCH) decoder in communication with the HSDPA despreader and the CLEPP;
• and
• (e) a channel quality indicator (CQI) estimator in communication with the HSDPA despreader for providing CQI information to the modem host.

An integrated circuit (IC) for enhancing the capabilities of a modem host in a wireless transmit/receive unit (WTRU), the IC comprising:

• (a) a Rake receiver for receiving in-phase (I)/quadrature (Q) samples;
• (b) a high speed downlink packet access (HSDPA) despreader in communication with an output of the Rake receiver;
• (c) a chip level equalizer post processor (CLEPP) in communication with the Rake receiver and the HSDPA despreader;
• (d) a high speed shared control channel (HS-SCCH) decoder in communication with the HSDPA despreader and the CLEPP;
• and
• (e) a channel quality indicator (CQI) estimator in communication with the HSDPA despreader for providing CQI information to the modem host.