Method and apparatus for processing a complete burst of data

A system for processing a complete burst of data comprising:

• ingress interface capable of receiving a complete burst of data;
• egress interface capable of transmitting a complete burst of data;
• processor capable of executing an instruction sequence;
• memory capable of storing an instruction sequence and at least one of a portion of a complete burst of data and a complete burst of data;
• one or more instruction sequences stored in the memory including:
• burst receiver module that, when executed by the processor, minimally causes the processor to:
• receive a complete burst of data from the ingress interface;
• and
• store the complete burst of data in the memory in association with a first logical channel;
• burst dispatch module that, when executed by the processor, minimally causes the processor to:
• retrieve from the memory one or more complete bursts of data;
• generate an egress burst of data according to the retrieved one or more bursts of data;
• and
• direct the egress burst of data to the egress interface.

A burst data interface controller comprising:

• memory interface capable of interacting with a memory;
• burst receive unit capable of receiving a complete burst of data from an ingress interface;
• memory control unit capable of enabling the receive burst unit to store a complete burst of data in a memory using the memory interface according to a logical channel association;
• and
• transmit burst unit capable of retrieving one or more bursts of data from a memory using the memory interface and further capable of directing the one or more bursts of data to an egress interface.