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US 2006/0039232 A1Published application
Read command triggered synchronization circuitry
AssigneeMicron Technology, Inc.
InventorJoo Choi
Life of this patent
Estimating the term…
Abstract
A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off.
Claims20
A method of controlling a clock synchronization circuit in a memory device, said method comprising:
- receiving a command to read data from said memory device;
- turning on said clock synchronization circuit to produce an output clock signal in response to said receiving;
- synchronizing said output clock signal with a reference clock signal;
- reading said data from said memory device after said synchronizing;
- and
- turning off said clock synchronization circuit after said reading.
3 more elements
A method of controlling a clock synchronization circuit in a memory device, said method comprising:
- receiving a command to read data from said memory device;
- signaling said clock synchronization circuit to turn on in response to said receiving;
- locking said clock synchronization circuit to a reference clock signal;
- reading said data from said memory device after said locking;
- and
- signaling said clock synchronization circuit to turn off in response to completion of said reading.
3 more elements
A method of controlling a clock synchronization circuit in a memory device, said method comprising:
- deactivating said clock synchronization circuit;
- receiving a read command;
- activating said clock synchronization circuit;
- reading data in accordance with said read command;
- and
- deactivating said clock synchronization circuit in response to completion of said reading.
3 more elements
A memory device comprising:
- a memory array operative to store data;
- a controller operative to receive commands to read said stored data from said memory array;
- a clock synchronization circuit operative to receive a reference clock signal and to output a synchronized clock output signal;
- and
- a signal line coupling said controller to said clock synchronization circuit, said signal line operative to convey signals from said controller to said clock synchronization circuit to turn on said synchronization circuit in response to said controller receiving a read command and to turn off said synchronization circuit after said reading.
2 more elements
A memory device comprising:
- a memory array having an array of control inputs operative to receive control signals and having an array of data inputs and outputs, said inputs operative to receive data and said outputs operative to output data;
- I/O logic having an array of control inputs operative to receive control signals, a first array of data inputs and outputs coupled to said memory array data inputs and outputs, and a second array of data inputs and outputs, said I/O logic operative to receive data from said memory array and output said data from said second array, said I/O logic also operative to receive data from said second array and output said data to said memory array;
- control logic having an array of inputs operative to receive instructions and an array of control outputs, a portion of said outputs coupled to said memory array and a portion of said outputs coupled to said I/O logic, said control logic operative to control said memory array and said I/O logic;
- WRITE logic having an array of data inputs operative to receive data and an array of data outputs operative to transmit data to said I/O logic second array;
- and
- READ logic having an array of data inputs operative to receive data from said I/O logic second array and an array of data outputs operative to output said data, said READ logic further comprising:
- clock synchronization circuit operative to control the timing of said receiving data, wherein said clock synchronization circuit is turned on and off by said control logic.
4 more elements
Apparatus for controlling a clock synchronization circuit in a memory device, said apparatus comprising:
- means for receiving a command to read data from said memory device;
- means for turning on said clock synchronization circuit to produce an output clock signal in response to said receiving;
- means for synchronizing said output clock signal with a reference clock signal;
- means for reading said data from said memory device after said synchronizing;
- and
- means for turning off said clock synchronization circuit after said reading.
3 more elements
Apparatus for controlling a clock synchronization circuit in a memory device, said apparatus comprising:
- means for receiving a command to read data from said memory device;
- means for signaling said clock synchronization circuit to turn on in response to said receiving;
- means for locking said clock synchronization circuit to a reference clock signal;
- means for reading said data from said memory device after said locking;
- and
- means for signaling said clock synchronization circuit to turn off in response to completion of reading said data.
3 more elements
Apparatus for controlling a clock synchronization circuit in a memory device, said apparatus comprising:
- means for deactivating said clock synchronization circuit;
- means for receiving a read command;
- means for activating said clock synchronization circuit;
- means for reading data in accordance with said read command;
- and
- means for deactivating said clock synchronization circuit in response to completion of said reading.
3 more elements
A system comprising:
- a processor;
- a memory controller coupled to said processor;
- a plurality of dynamic random access memory (DRAM) chips coupled to said memory controller, at least one of said DRAM chips comprising a clock synchronization circuit operative to receive a reference clock signal and to output a synchronized clock output signal;
- a plurality of signal buses coupling said processor to said memory controller and said memory controller to said DRAM chips;
- and
- a signal line coupling said memory controller to said clock synchronization circuit, said signal line conveying signals from said memory controller to said clock synchronization circuit to turn said clock synchronization circuit on in response to said controller receiving a read command and to turn said clock synchronization circuit off after said read command is processed.
3 more elements
Dependencies are inferred from the claim text.