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US 2006/0039208 A1Published application
Metal-poly integrated capacitor structure
AssigneeMicron Technology, Inc.
InventorGiulio Marotta
Life of this patent
Estimating the term…
Abstract
A metal-poly integrated capacitor structure that may be used in a charge pump circuit of a non-volatile memory. In one embodiment, the capacitor comprises a poly silicon layer, a first metal layer and a second metal layer. The first metal layer is positioned between the poly silicon layer and the second metal layer. The first metal layer has a first terminal and a second terminal. The first terminal is electrically isolated from the second terminal.
Claims20
A non-volatile memory device comprising:
- a memory array of non-volatile memory cells to store data;
- control circuitry to control memory operations to the memory array;
- an address register to selectively couple address requests to the memory array;
- an input/output buffer to smooth out data flowing to and from the memory array;
- and
- a charge pump circuit to boost voltage levels during select memory operations, the charge pump circuit having capacitors, each capacitor including,
- a poly silicon layer,
- a second metal layer, and
- a first metal layer positioned between the poly silicon layer and the second metal layer, the first metal layer having a first terminal and a second terminal, wherein the first terminal is electrically isolated from the second terminal.
6 more elements
A non-volatile memory device comprising:
- a memory array of non-volatile memory cells to store data;
- control circuitry to control memory operations to the memory array;
- and
- a charge pump circuit to boost voltage levels during select memory operations, the charge pump circuit comprising:
- a charge pump for generating an output voltage signal;
- a first capacitor having a first and second terminal;
- a second capacitor having a first and second terminal, the first terminal of the second capacitor is coupled to the first terminal of the first capacitor;
- wherein each of the first and second capacitors comprises:
- a poly silicon layer;
- a second metal layer;
- and
- a first metal layer positioned between the poly silicon layer and the second metal layer, the first metal layer having the first terminal and the second terminal, the first terminal is electrically isolated from the second terminal;
- a first transistor coupled to selectively couple the second terminal of the first capacitor to receive the output signal of the charge pump;
- a second transistor coupled between the second terminal of the first capacitor and ground;
- a third transistor coupled between the first terminals of the first and second transistors and ground, wherein gates of the first, second and third transistors are coupled to receive a reset signal;
- a differential amplifier having a first input coupled to the first terminals of the first and second capacitors, the differential amplifier having a second input coupled to receive a voltage reference;
- and
- an AND gate having a first input coupled to an output of the differential amplifier and a second input coupled to receive a clock pulse, an output of the AND gate is coupled to an input of the charge pump.
15 more elements
A non-volatile memory device comprising:
- a memory array of non-volatile memory cells to store data;
- control circuitry to control memory operations to the memory array;
- and
- a charge pump circuit to boost voltage levels during select memory operations, the charge pump circuit comprising:
- a charge pump for generating an output voltage signal;
- a first capacitor having a first and second terminal;
- a second capacitor having a first and second terminal, the first terminal of the second capacitor is coupled to the first terminal of the first capacitor;
- wherein each of the first and second capacitors comprises:
- a first metal layer forming the first and second terminals, the first and second terminals each having a base strip and a plurality of side strips that extend from the respective base strip, wherein the side strips of the first terminal are positioned in between the side strips of the second terminal so that the first and second side strips are alternately positioned between the first and second bases of the respective first and second terminals;
- a second metal layer;
- and
- a poly silicon layer, the first metal layer is positioned between the poly silicon layer and the second metal layer;
- a first transistor coupled to selectively couple the second terminal of the first capacitor to receive the output signal of the charge pump;
- a second transistor coupled between the second terminal of the first capacitor and ground;
- a third transistor coupled between the first terminals of the first and second transistors and ground, wherein gates of the first, second and third transistors are coupled to receive a reset signal;
- a differential amplifier having a first input coupled to the first terminals of the first and second capacitors, the differential amplifier having a second input coupled to receive a voltage reference;
- and
- an AND gate having a first input coupled to an output of the differential amplifier and a second input coupled to receive a clock pulse, an output of the AND gate is coupled to an input of the charge pump.
15 more elements
A non-volatile memory device comprising:
- a memory array to store data;
- control circuitry to control memory operations to the memory array;
- and
- a charge pump circuit to boost voltage levels during select memory operations, the charge pump circuit comprising:
- a charge pump for generating an output voltage signal;
- a first capacitor having a first and second terminal;
- a second capacitor having a first and second terminal, the first terminal of the second capacitor is coupled to the first terminal of the first capacitor;
- wherein each of the first and second capacitors comprises:
- a poly silicon layer;
- the first metal terminal formed over the poly silicon layer and having a first base strip and a plurality of first side strips extending from the first base strip;
- the second metal terminal formed over the poly silicon layer and having a second base strip and a plurality of second side strips extending from the second base strip, the second metal terminal electrically isolated from the first metal terminal and electrically coupled to the poly silicon layer;
- and
- a metal layer formed over the first and second metal terminals and electrically coupled to the second metal terminal;
- a first transistor coupled to selectively couple the second terminal of the first capacitor to receive the output signal of the charge pump;
- a second transistor coupled between the second terminal of the first capacitor and ground;
- a third transistor coupled between the first terminals of the first and second transistors and ground, wherein gates of the first, second and third transistors are coupled to receive a reset signal;
- a differential amplifier having a first input coupled to the first terminals of the first and second capacitors, the differential amplifier having a second input coupled to receive a voltage reference;
- and
- an AND gate having a first input coupled to an output of the differential amplifier and a second input coupled to receive a clock pulse, an output of the AND gate is coupled to an input of the charge pump.
16 more elements
A flash memory system comprising:
- a processor to provide external data;
- a memory array to store the external data;
- control circuitry to control memory operations to the memory array, the control circuitry coupled to receive control commands from the processor;
- an address register to selectively couple address requests to the memory array;
- an input/output buffer to smooth out data flowing to and from the memory array;
- and
- a charge pump circuit to boost voltage levels during select memory operations, the charge pump circuit having a first and second capacitor, each capacitor including,
- a first metal layer forming first and second terminals, the first and second terminals each having a base strip and a plurality of side strips that extend from the respective base strip, wherein the side strips of the first terminal are positioned in between the side strips of the second terminal so that the first and second side strips are alternately positioned between the first and second bases of the respective first and second terminals,
- a second metal layer, and
- a poly silicon layer, the first metal layer is positioned between the poly silicon layer and the second metal layer.
7 more elements
A flash memory system comprising:
- a processor;
- a memory array coupled to the processor;
- control circuitry to control memory operations to the memory array, the control circuitry coupled to receive control commands from the processor;
- and
- a charge pump circuit to boost voltage levels during select memory operations, the charge pump circuit comprising:
- a charge pump for generating an output voltage signal;
- a first capacitor having a first and second terminal;
- a second capacitor having a first and second terminal, the first terminal of the second capacitor is coupled to the first terminal of the first capacitor;
- wherein each of the first and second capacitors comprises:
- a poly silicon layer;
- the first metal terminal formed over the poly silicon layer and having a first base strip and a plurality of first side strips extending from the first base strip;
- the second metal terminal formed over the poly silicon layer and having a second base strip and a plurality of second side strips extending from the second base strip, the second metal terminal electrically isolated from the first metal terminal and electrically coupled to the poly silicon layer;
- and
- a metal layer formed over the first and second metal terminals and electrically coupled to the second metal terminal;
- a first transistor coupled to selectively couple the second terminal of the first capacitor to receive the output signal of the charge pump;
- a second transistor coupled between the second terminal of the first capacitor and ground;
- a third transistor coupled between the first terminals of the first and second transistors and ground, wherein gates of the first, second and third transistors are coupled to receive a reset signal;
- a differential amplifier having a first input coupled to the first terminals of the first and second capacitors, the differential amplifier having a second input coupled to receive a voltage reference;
- and
- an AND gate having a first input coupled to an output of the differential amplifier and a second input coupled to receive a clock pulse, an output of the AND gate is coupled to an input of the charge pump.
17 more elements
A flash memory system comprising:
- a processor;
- a memory array coupled to the processor;
- control circuitry to control memory operations to the memory array, the control circuitry coupled to receive control commands from the processor;
- and
- a charge pump circuit to boost voltage levels during select memory operations, the charge pump circuit comprising:
- a charge pump for generating an output voltage signal;
- a first capacitor having a first and second terminal;
- a second capacitor having a first and second terminal, the first terminal of the second capacitor is coupled to the first terminal of the first capacitor;
- wherein each of the first and second capacitors comprises:
- a poly silicon layer;
- a second metal layer;
- and
- a first metal layer positioned between the poly silicon layer and the second metal layer, the first metal layer having the first terminal and the second terminal, the first terminal is electrically isolated from the second terminal;
- a first transistor coupled to selectively couple the second terminal of the first capacitor to receive the output signal of the charge pump;
- a second transistor coupled between the second terminal of the first capacitor and ground;
- a third transistor coupled between the first terminals of the first and second transistors and ground, wherein gates of the first, second and third transistors are coupled to receive a reset signal;
- a differential amplifier having a first input coupled to the first terminals of the first and second capacitors, the differential amplifier having a second input coupled to receive a voltage reference;
- and
- an AND gate having a first input coupled to an output of the differential amplifier and a second input coupled to receive a clock pulse, an output of the AND gate is coupled to an input of the charge pump.
16 more elements
Dependencies are inferred from the claim text.