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US 2006/0039183 A1Published application
Multi-sensing level MRAM structures
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWen Lin, Denny Tang, Chien-Chung Hung, Wen-Chin Lee
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Abstract
A memory cell including a switching element having a source and a drain, a first magnetic tunnel junction (MTJ) device, and a second MTJ device. The first MTJ device has a first tunneling junction resistance and is coupled to a first one of the switching element source and drain. The second MTJ device has a second tunneling junction resistance and is coupled to a second one of the switching element source and drain. The second resistance is substantially less than the first resistance.
Claims21
A memory cell comprising:
- a switching element having a source and a drain;
- a first magnetic tunnel junction (MTJ) device having a first tunneling junction resistance and coupled to a first one of the switching element source and drain;
- and
- a second MTJ device having a second tunneling junction resistance and coupled to a second one of the switching element source and drain, wherein the second resistance is substantially less than the first resistance.
1 more element
A memory cell, comprising:
- a biasing conductor;
- a first MTJ device including a first free layer, a first pinned layer, and a first tunneling barrier interposing the first free and pinned layers thereby defining a first contact area between the first tunneling barrier and each of the first free and pinned layers, wherein the first free layer is electrically coupled to the biasing conductor;
- a second MTJ device including a second free layer, a second pinned layer, and a second tunneling barrier interposing the second free and pinned layers thereby defining a second contact area between the second tunneling barrier and each of the second free and pinned layers, the second contact area being substantially quantitatively different than the first contact area, wherein the second free layer is electrically coupled to the biasing conductor;
- and
- a switching device having a source and a drain, wherein a first one of the source and drain is electrically coupled to the first pinned layer and a second one of the source and drain is electrically coupled to the second pinned layer.
2 more elements
A memory cell, comprising:
- a biasing conductor;
- a first MTJ device including a first free layer, a first pinned layer, and a first tunneling barrier having a first thickness and interposing the first free and pinned layers, wherein the first free layer is electrically coupled to the biasing conductor;
- a second MTJ device including a second free layer, a second pinned layer, and a second tunneling barrier having a second thickness and interposing the second free and pinned layers, wherein the second thickness is substantially different than the first thickness, and wherein the second free layer is electrically coupled to the biasing conductor;
- and
- a switching device having a source and a drain, wherein a first one of the source and drain is electrically coupled to the first pinned layer and a second one of the source and drain is electrically coupled to the second pinned layer.
2 more elements
A memory cell, comprising:
- a biasing conductor;
- a first MTJ device including a first free layer, a first pinned layer, and a first tunneling barrier interposing the first free and pinned layers, the first free layer electrically coupled to the biasing conductor;
- a second MTJ device including a second free layer, a second pinned layer, a second tunneling barrier interposing the second free and pinned layers, a third free layer, a third pinned layer, and a third tunneling barrier interposing the third free and pinned layers, the third free layer contacting the second pinned layer, the second free layer electrically coupled to the biasing conductor;
- and
- a switching device having a source and a drain, wherein a first one of the source and drain is electrically coupled to the first pinned layer and a second one of the source and drain is electrically coupled to the third pinned layer.
2 more elements
A memory cell, comprising:
- a biasing conductor;
- a switching device having a source and a drain;
- a first MTJ device including a first free layer, a first pinned layer, and a first tunneling barrier interposing the first free and pinned layers, wherein the first MTJ device is electrically coupled between the biasing conductor and a first one of the source and drain of the switching device;
- a second MTJ device including a second free layer, a second pinned layer, and a second tunneling barrier interposing the second free and pinned layers, wherein the second MTJ device is electrically coupled between the biasing conductor and a second one of the source and drain of the switching device;
- and
- a resistive element electrically coupled in series with the second MTJ device between the biasing conductor and the switching device.
3 more elements
Dependencies are inferred from the claim text.