Content addressable memory

Abstract

The present invention provides a content addressable memory (CAM) with no problem in operation speed reduction and with small power consumption on an SOI substrate. The CAM includes a data memory part DM and a data comparison part DC which compares data provided on a search line SL with data stored in the data memory part DM. In the case of a mismatch, a match line ML precharged to H level is discharged to be L level. Here, gates and bodies of respective NMOS transistors N6 and N8, which constitute data comparison part DC, are short-circuited to lower threshold voltages of NMOS transistors N6 and N8. Therefore, even if lowering of voltage of search line SL connected to gate is performed, turn-on current of MOS transistors N6 and N8 can be increased to discharge the match line ML with high speed. As a result, even if lowering of power consumption of the search line SL is performed to lower power consumption, a CAM with no problem in operation speed reduction can be realized.

Dependencies are inferred from the claim text.