Redundancy in column parallel or row architectures
AssigneeMicron Technology, Inc.
InventorChristian Boemler
Life of this patent
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Abstract
A column circuitry architecture for an imager includes redundant column or row circuits. The column or row circuitry includes a number of redundant column or row circuits. Each column or row circuit include circuitry for controllably coupling the column or row circuit to one of plural signal lines from an array of pixels. A control mechanism is used to select a configuration of plural column or row circuits in the column or row circuitry. In this manner, some column or row circuits are decoupled from the pixel in favor of other column or row circuits. The decoupled column or row circuits may include defective or noisy circuits.
Claims39
A circuit for processing pixel signals from N pixels, comprising:
- M signal processing circuits, each of said M signal processing circuits being configurable to receive pixel signals from a plurality of said N pixels;
- a control circuit coupled to each of said M signal processing circuits, for configuring each of said M signal processing circuits;
- and
- M column decoders, respectively coupled between said control circuit and said M signal processing circuits;
- wherein M is greater than N.
An imager, comprising:
- a pixel array, comprising a plurality of pixels arranged into a plurality of rows and N columns;
- a row selector for selecting N pixels from one of said plurality of rows;
- and
- a circuit for processing pixel signals received from a selected row of N pixels, comprising:
- M signal processing circuits, each of said M signal processing circuits being configurable to receive pixel signals from a plurality of said N pixels;
- a control circuit coupled to each of said M signal processing circuits, for configuring each of said M signal processing circuits;
- and
- M column decoders, respectively coupled between said control circuit and said M signal processing circuits;
- wherein M is greater than N.
A circuit for driving one of N rows of pixels in an imager, comprising:
- M row driving circuits, each of said M row driving circuits being configurable to drive one of the N rows of pixels;
- a control circuit coupled to each row driving circuit, for configuring each row driving circuit and for generating a row address corresponding to said one row;
- and
- M row decoders respectively coupled between said control circuit and each of said M row driving circuits;
- wherein M is greater than N, and N is greater than one.
A method of processing pixel signals from N pixels, comprising:
- configuring, from a set of M signal processing circuits, a subset of N signal processing circuits to each respectively receive pixels signals from said N pixels;
- sampling and holding, at each signal processing circuit in said subset, pixel signals from a respective one of said N pixels;
- and
- sequentially selecting different ones of said signal processing circuits in said subset to output said sampled and held pixel signals of said selected signal processing circuit;
- wherein M is greater than N, and N is greater than one.
A method of driving one of N rows of pixels, comprising:
- configuring, from a set of M row driving circuits, a subset of N row driving circuits, each to respectively drive a different one of said N rows;
- receiving a row address;
- and
- operating one of said row driving circuits in said subset to drive one of said rows of pixels associated with said row address;
- wherein M is greater than N, and N is greater than one.
Dependencies are inferred from the claim text.