Gate line driving circuit
OwnerTetsuya Nakamura, Seiji Kawaguchi +1inventors
InventorsTetsuya Nakamura, Seiji Kawaguchi, Masahiko Takeoka
Life of this patent
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Abstract
A gate line driving circuit includes a shift register section that selects gate lines for gradation display and for black insertion, and an output circuit that outputs a driving signal to the gate line which is selected by the shift register section. In particular, the output circuit is configured to obtain an overlap between an output period of a driving signal to each selected gate line and an output period of a driving signal to a gate line that is driven in precedence to the selected gate line, and independently control a first preliminary driving period corresponding to the overlap for gradation display and a second preliminary driving period corresponding to the overlap for black insertion.
Claims5
A gate line driving circuit that drives a plurality of gate lines, which are assigned to rows of pixels arranged substantially in a matrix, said gate line driving circuit comprising:
- a selecting section that selects the gate lines for gradation display and for non-gradation display;
- and
- an output circuit that outputs a driving signal to the gate line which is selected by the selecting section, said output circuit being configured to obtain an overlap between an output period of a driving signal to each selected gate line and an output period of a driving signal to a gate line that is driven in precedence to the selected gate line, and independently control a first preliminary driving period during which the output period of the driving signal to the gate line selected for gradation display overlaps the output period of the driving signal to the gate line that is driven in precedence to the gate line selected for the gradation display, and a second preliminary driving period during which the output period of the driving signal to the gate line selected for non-gradation display overlaps the output period of the driving signal to the gate line that is driven in precedence to the gate line selected for the non-gradation display.
Dependencies are inferred from the claim text.