Electronic access control device

An apparatus comprising:

• a first circuit comprising an oscillator and having a first circuit output signal;
• a second circuit enabled and disabled in response to the first circuit output signal, the second circuit having a second circuit output signal generated in response to receipt of an electromagnetic signal;
• a third circuit enabled during the receipt of the electromagnetic signal, the circuit having a third circuit output signal comprising an input code generated in response to receipt of an electromagnetic signal;
• a fourth circuit enabled during an operation mode to compare the input code to an authorization code and having a sleep mode to conserve power;
• and,
• a driver having an output that is provided to a device if the input code matches the authorization code.

An apparatus comprising:

• an oscillator having an output comprising a plurality of duty cycles;
• a circuit that is periodically enabled for a time t1 and disabled for a time t2 during at least some of the duty cycles;
• a portion of the circuit that generates an input code in response to an electromagnetic signal;
• a microprocessor that compares the input code to an authorization code during an operation mode and having a sleep mode to conserve power;
• a device responsive to a signal generated by the microprocessor, the device comprising at least one of the following:
• a solenoid;
• an electromechanical relay;
• a DC motor;
• a solid-state relay;
• and, an alarm.

A method comprising the steps of:

• deactivating a circuit during a first time period;
• enabling a portion of the circuit for a second time period;
• sensing an electromagnetic signal during the second time period;
• processing the electromagnetic signal to obtain an input code;
• comparing the input code to an authorization code during an operation mode and conserving power during a sleep mode;
• and,
• providing a signal to a device if the input code matches the authorization code.

A method comprising the steps of:

• periodically enabling and disabling a circuit during each of a plurality of duty cycles wherein the circuit is enabled for a time t1 during each of the duty cycles;
• receiving an input code transmitted via an electromagnetic signal;
• comparing the input code to an authorization code during an operation mode and conserving power during a sleep mode;
• enabling the circuit as the input code is being received for a time t2;
• and,
• providing a signal to a device if the input code matches the authorization code.

A method comprising the steps of:

• permanently storing a non-reprogrammable and permanent access code within a non-volatile memory;
• providing a wake-up signal in response to pressing a key on a keypad;
• waking-up at least one microprocessor for a period of time in response to the wake-up signal;
• transmitting an input code to a microprocessor;
• comparing the input code with a stored access code during the period of time;
• activating a lock actuator if the input code matches the stored access code;
• entering a sleep mode after the period of time, wherein during the sleep mode the microprocessor operates at a lower power consumption rate than when the microprocessor is awake.

An apparatus comprising:

• a non-volatile memory containing a non-reprogrammable and substantially permanently stored access code;
• a circuit generating a wake-up signal in response to pressing a key on a keypad;
• at least one processor that is woke-up for a period of time in response to the wake-up signal, compares an input code with a stored access code, and generates a signal to activate a lock actuator if the input code matches a stored access code;
• wherein at least one processor enters a sleep mode after the period of time, the sleep mode causing the processor to operate at a lower power consumption rate than when the processor is awake.

An apparatus comprising:

• a non-volatile memory containing a non-reprogrammable and substantially permanently stored access code;
• circuitry comprising two processors wherein at least one of the processors is shielded from external access;
• a portion of the circuitry generating a wake-up signal in response to pressing a key on a keypad;
• at least one of the processors being woke-up in response to the wake-up signal and receiving an input code;
• at least one of the processors being woke-up and comparing the input code with the stored access code;
• at least one of the processors generating a signal to activate a lock actuator if the input code matches the stored access code;
• wherein at least one of the processors enters a sleep mode wherein the processor operates at a lower power consumption rate than when the processor is awake.

An apparatus comprising:

• a non-volatile memory containing a stored access code;
• a circuit comprising two processors wherein at least one of the processors is shielded from external access;
• a portion of the circuitry generating a wake-up signal in response to pressing a key on a keypad;
• at least one of the processors being woke-up in response to the wake-up signal and receiving an input code;
• at least one of the processors being woke-up and comparing the input code with the stored access code;
• at least one of the processor generating a signal to activate a lock actuator if the input code matches the stored access code;
• at least a portion of the circuitry comprising a low battery detection circuit that is enabled by one of the processors in an operation mode and disabled in a sleep mode, the low battery detection circuit measuring a voltage of a battery in the operation mode;
• and,
• wherein at least one of the processors enters a sleep mode wherein the processor operates at a lower power consumption rate than when the processor is awake.

An apparatus comprising:

• a non-volatile memory containing a stored access code;
• a circuit comprising two processors wherein at least one of the processors is shielded from external access;
• at least a portion of the circuit generating a wake-up signal in response to pressing a key on a keypad;
• at least one of the processors being woke-up in response to the wake-up signal and receiving an input code;
• at least one of the processors being woke-up and comparing the input code with the stored access code;
• at least one of the processors generating a signal to activate a solenoid if the input code matches the stored access code;
• at least a portion of the comprising a solenoid control circuit for energizing a solenoid, the solenoid control circuit being controlled by at least one of the processors and being enabled when the processor is in an operation mode, the solenoid control circuit having first and second energized states controlled by a timer to energize the solenoid in the first energized state for a pre-selected first time interval at a first power level to move a plunger of the solenoid into a retracted position, and subsequently to energize the solenoid in the second energized state at a second power level to maintain the plunger in the retracted position for a second pre-selected time interval, the second power level being non-zero and lower than the first power level;
• and,
• wherein at least one of the processors enters a sleep mode wherein processor operates at a lower power consumption rate than when the processor is awake.