Clock signal generators having programmable full-period clock skew control

An integrated circuit device, comprising:

• an integrated circuit chip having a clock driver therein that supports generation of a plurality of output clock signals having different frequencies in a range between 1 and 1/N times a frequency of an internal clock signal and full-period programmable skew characteristics, where N is a positive integer greater than one;
• wherein the clock driver comprises an internal clock signal generator selected from the group consisting of a phase-locked loop (PLL) integrated circuit and a delay-locked loop (DLL) integrated circuit;
• wherein the clock driver is configured to support generation of a divide-by-N clock signal having a full-period programmable skew characteristics that is stepped in N×M time units having a duration equal to 1/M times a period of the internal clock signal, where M is a positive integer greater than eight;
• and
• wherein the clock driver comprises:
• a divide-by-N clock generator responsive to a periodic signal;
• and
• a synchronization unit electrically coupled to an output of said divide-by-N clock generator.

An integrated circuit chip, comprising:

• a locked loop integrated circuit configured to generate a plurality of internal clock signals that are skewed in time relative to each but have the same first frequency;
• a skew signal select circuit configured to generate a selected skew signal derived from at least one of the plurality of internal clock signals;
• a divide-by-N clock generator circuit configured to generate at least a first divide-by-N clock signal in response to a first periodic signal generated by said locked loop integrated circuit, where N is a positive integer greater than one;
• a synchronization unit configured to generate a second periodic signal that is synchronized to the selected skew signal and has a frequency equal to a frequency of the first divide-by-N clock signal;
• and
• an output buffer configured to drive an off-chip load with an output clock signal having a full-period skew characteristic, in response to the second periodic signal.