Systems and methods for implementing delay line circuitry
AssigneeL-3 Integrated Systems Company
InventorsBradley Avants, Arturo Yanez
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Abstract
Memory devices used to control delay line circuitry, and that may be implemented in one embodiment to provide a self-tuning delay line device using empirical calibration technique/s to achieve a desired signal delay. The memory control device may be implemented to store electrical characteristics of the delay line circuitry during testing to enable self-calibration of the delay line circuitry.
Claims48
Delay line circuitry configured to receive and delay an input signal to produce a delayed output signal, said delay line circuitry comprising:
- a plurality of delay elements;
- and
- delay element control circuitry configured to control said plurality of delay elements to produce said delayed output signal based at least in part on delay element setting information provided by at least one memory device.
Delay line circuitry configured to receive and delay an input signal to produce a delayed output signal, said delay line circuitry comprising:
- a plurality of delay elements;
- and
- delay element control circuitry configured to control said plurality of delay elements to produce said delayed output signal, said delay element control circuitry comprising at least one memory device.
A phased array apparatus, comprising:
- a plurality of array elements;
- and
- a plurality of phase shifting devices, each of said plurality of phase shifting devices being coupled to a respective one of said plurality of array elements;
- wherein each of said plurality of phase shifting devices comprises a plurality of delay elements, and delay element control circuitry configured to control said plurality of delay elements based at least in part on delay element setting information provided by at least one memory device.
A method of delaying an input signal to produce a delayed output signal using a plurality of delay elements coupled to receive and delay said input signal to produce said delayed output signal, said method comprising controlling said plurality of delay elements to produce said delayed output signal based at least in part on delay element setting information provided by at least one memory device.
A method of operating a phased array apparatus, comprising:
- providing a plurality of array elements;
- and
- providing a plurality of phase shifting devices, each of said plurality of phase shifting devices comprising a plurality of delay elements and being coupled to a respective one of said plurality of array elements;
- varying the phase of a signal transmitted or received by each respective one of said array elements by controlling said plurality of delay elements of said respective phase shifting device coupled to said respective array element based at least in part on delay element setting information provided by at least one memory device.
Test circuitry configured for coupling to delay line circuitry that has a plurality of delay elements and that has delay element control circuitry configured to control said plurality of delay elements to produce a delayed output signal based at least in part on delay element setting information provided by at least one memory device, said test circuitry comprising:
- circuitry configured to derive said delay element setting information for storage in said memory device.
Dependencies are inferred from the claim text.