Delay locked loop circuitry and method for optimizing delay timing in mixed signal systems

A monolithic integrated circuit mixed signal system comprising:

• (a) a digital circuit including a clock input for receiving a digital clock signal;
• (b) an analog circuit including an input for receiving an analog clock signal;
• (c) clock generation circuitry including
• i. a delay locked loop including a N-cell delay line having an input for receiving a reference clock signal and also including a plurality of delay outputs, and
• ii. a multiplexer having a plurality of inputs coupled to the plurality of delay outputs, respectively, and a selection input for receiving a selection signal for causing the multiplexer to couple a selected one of the delay outputs to an output of the multiplexer;
• (d) the digital circuit causing coupling of a noise glitch to the analog circuit;
• (e) the reference clock signal being utilized as one of the digital clock signal and the analog clock signal;
• (f) the output of the multiplexer producing the other of the digital clock signal the analog clock signal;
• and
• (g) the selection input signal of the multiplexer causing the analog clock signal and the digital clock signal to be sufficiently skewed from each other to minimize an inaccuracy in the analog circuit caused by the coupling of the noise glitch thereto.

A method of operating a mixed signal system in an integrated circuit chip to avoid degradation of an analog signal due to noise caused by a digital signal, the mixed signal system including a digital circuit including a clock input for receiving a digital clock signal and also including an analog circuit including a clock input for receiving an analog clock signal wherein a digital signal associated with the digital circuitry causes coupling of a noise glitch to the analog circuit, the method comprising:

• (a) applying a reference clock signal to a clock input of a delay locked loop having a plurality of delay outputs,
• (b) operating the delay locked loop in response to the reference clock signal to force a signal delay time through a delay line of the delay locked loop to be equal to a period of the reference clock signal;
• (b) coupling one of the delay outputs to an output of the delay locked loop;
• and
• (c) using the reference clock signal as one of the digital clock signal and the analog clock signal, the output of the multiplexer producing the other of the digital clock signal and the analog clock signal, the analog clock signal and the digital clock signal being sufficiently skewed from each other to minimize an inaccuracy in the analog circuit caused by the coupling of the noise glitch thereto.

A method of operating a mixed signal system in an integrated circuit chip to avoid degradation of an analog signal due to noise caused by a digital signal, the mixed signal system including a digital circuit including a clock input for receiving a digital clock signal and also including an analog circuit including a clock input for receiving an analog clock signal, wherein a digital signal associated with the digital circuitry causes coupling of a noise glitch to the analog circuit, the method comprising:

• (a) applying a reference clock signal to a clock input of a delay locked loop having a plurality of delay outputs;
• (b) coupling the plurality of delay outputs to a plurality of inputs, respectively, of a multiplexer having a selection input for receiving a selection signal for causing the multiplexer to couple a selected one of the delay outputs to an output of the multiplexer;
• (c) using the reference clock signal as one of the digital clock signal and the analog clock signal, the output of the multiplexer producing the other of the digital clock signal and the analog clock signal;
• and
• (d) providing the selection input signal of the multiplexer so as to cause the analog clock signal and the digital clock signal to be sufficiently skewed from each other to minimize an inaccuracy in the analog circuit caused by the coupling of the noise glitch thereto.

A mixed signal system in an integrated circuit chip, comprising:

• (a) a digital circuit including a clock input for receiving a digital clock signal and also including an analog circuit including a clock input for receiving an analog clock signal, wherein a digital signal associated with the digital circuitry causes coupling of a noise glitch to the analog circuit;
• (b) means for applying a reference clock signal to a clock input of a delay locked loop having a plurality of delay outputs;
• (c) means for coupling one of the delay outputs to an output of the delay locked loop;
• and
• (d) means for using the reference clock signal as one of the digital clock signal and the analog clock signal, the output of the multiplexer producing the other of the digital clock signal and the analog clock signal, the analog clock signal and the digital clock signal being sufficiently skewed from each other to minimize an inaccuracy in the analog circuit caused by the coupling of the noise glitch thereto.

A mixed signal system in an integrated circuit chip, comprising:

• (a) a digital circuit including a clock input for receiving a digital clock signal and also including an analog circuit including a clock input for receiving an analog clock signal, wherein a digital signal associated with the digital circuitry causes coupling of a noise glitch to the analog circuit;
• (b) means for applying a reference clock signal to a clock input of a delay locked loop having a plurality of delay outputs;
• (c) means for coupling one of the delay outputs to an optimized clock conductor in response to a selection signal;
• (d) means for using the reference clock signal as one of the digital clock signal and the analog clock signal, the optimized clock conductor providing the other of the digital clock signal and the analog clock signal;
• and
• (e) means for providing the selection input signal of the multiplexer so as to cause the analog clock signal and the digital clock signal to be sufficiently skewed from each other to minimize an inaccuracy in the analog circuit caused by the coupling of the noise glitch thereto.