Dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation

A logical control element for providing a window signal active between assertion of a control signal and a time at which a logical combination of one or more other signals assumes a predetermined state, said logical control element comprising:

• a dynamic logic tree formed from one or more transistor ladders comprising transistors having series connected channels coupled between a summing node and a first power supply rail corresponding to a first logical state, and wherein gates of said transistors are connected to said one or more other signals;
• a precharge circuit connected to said summing node and a second power supply rail for setting said summing node to a precharge voltage level corresponding to a second logical state opposite from said first logical state, said precharge circuit having an input coupled to said control signal, whereby said summing node is held in said second logical state while said control signal is deasserted;
• an inverter having an input coupled to said summing node and an inverter output providing said window signal at an output of said logical control element;
• and
• means for overriding the output of said inverter, whereby said output of said control element is held in a first logical output state corresponding to an evaluated state of said control element until said control signal is asserted.

A static-dynamic logic circuit having a control signal input and one or more logic inputs, comprising:

• a logic tree comprising one or more ladders of ladder transistors having series-connected channels, wherein a first end of each of said ladders is connected to a summing node of said static-dynamic logic circuit and a second end of each of said ladders is coupled to a first power supply rail, and wherein said ladder transistors have gates coupled to said one or more logic inputs;
• a first transistor having a first channel connection connected to an output of said static-dynamic logic circuit, a second channel connection connected to a second power supply rail and a gate connected to said control signal;
• a second transistor having a first channel connection connected to said first power supply rail and a gate connected to said control signal;
• a third transistor having a gate connected to said summing node, a first channel connection connected to a second channel connection of said second transistor and a second channel connection connected to said output;
• a fourth transistor having a gate connected to said summing node, a first channel connection connected to said second channels connection of said second transistor and a second channel connection connected to said output;
• a fifth transistor having a first channel connection connected to said summing node, a second channel connection connected to a second power supply rail and a gate connected to said control signal;
• and
• a sixth transistor having a first channel connection connected to said first power supply rail, a second channel connection connected to said second end of each of said ladders and a gate connected to said control signal.