Rf chip testing method and system
OwnerBrian Guthrie, Adrian Spencerinventors
Life of this patent
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Abstract
A method and system for testing RF chips for radio specification compliance is described. The system comprises a test board (80) having a plurality of interconnected sockets (82a,b,c) for receiving chips to be tested. In testing, signals generated by transmitter circuitry (20) within a group of test chips are used to test the receiver (30) functionality of the other chips loaded in the system. Hence, for tests requiring several analogue radio signals, a plurality of chips are tested at the same time using signals generated from other chips. Additionally, the system does not require expensive dedicated RF analogue signal generating equipment.
Claims12
A method for testing a plurality of integrated circuit chips for compliance with a radio standard, each chip having transmission means and receiving means for sending and receiving RF signals, the method comprising:
- placing the chips in close proximity to one another,
- testing (100) the transmission means of each chip with respect to a known good reference chip,
- selecting (104) a number of the chips to form a generating group, the remaining chips forming a receiving group, and
- testing the receiving group (106) using signals generated by the generating group.
A testing system for testing a plurality of integrated circuit chips, each chip having transmission means (10, 20) and receiving means (10, 30) for sending and receiving RF signals, the system comprising:
- a computer (40) having communication, control and data acquisition means (55) for communicating with, controlling and acquiring data from testing means to which it is connected,
- the testing means (80) comprising a plurality of chip sockets (82a, b, c) adapted to physically accept and electronically interface with a chip placed therein, and wherein each socket is provided with signal propagation (88) and attenuation means (86) for sending and receiving signals to each of the other sockets under the control of the computer (40),
- and where in operation the computer selects a group of chips (82b) to generate test signals which are propagated via the propagation means to a reception test group of chips (82a).
A test board (80) comprising a plurality of chip sockets (82a, b, c) adapted to physically accept and electronically interface with a chip placed therein, and wherein each socket is provided with signal propagation (88) and attenuation means (86) for sending and receiving test signals generated by at least one chip to each of the other sockets.
Dependencies are inferred from the claim text.