Methods and circuits for generating reference voltage

A circuit for generating a reference voltage for use in a semiconductor device, the circuit comprising:

• a first reference voltage generating circuit, disposed outside a first chip, configured to output a first reference voltage to a first output terminal;
• and
• a second reference voltage generating circuit, configured to output a second reference voltage to a second output terminal of the chip, wherein the second reference voltage generating circuit includes:
• at least one pull-up resistor, disposed inside the first chip, and coupled between a first node and the second output terminal, wherein the first node is electrically coupled to an internal power supply voltage of a first chip;
• at least one first pull-down resistor, disposed inside the first chip, and coupled to the second output terminal;
• a second pull-down resistor disposed inside a second chip and coupled to a ground;
• and
• a conductive line having a first impedance configured to be electrically coupled between the at least one first pull-down resistor and the second pull-down resistor, wherein a third reference voltage is outputted at a node where the first output terminal is electrically shorted to the second output terminal.

A semiconductor device comprising:

• a first input pad configured to receive a first reference voltage that is externally provided;
• a second input pad configured to receive a control voltage that is externally provided;
• at least one pull-up resistor coupled between a power supply voltage and a second output terminal, wherein a second reference voltage is outputted to the second output terminal;
• and
• at least one pull-down resistor coupled between the second output terminal and the second input pad, wherein the pull-up resistor and the first pull-down resistor have substantially the same resistance and wherein, the first reference voltage has a voltage level corresponding to a summed voltage of the control voltage and a voltage across the at least one pull-down resistor and wherein, a third reference voltage is outputted at a node where the first input pad is electrically shorted to the second output terminal.

A circuit for generating a reference voltage for use in a semiconductor device, the circuit comprising:

• a first reference voltage generating circuit, disposed outside a chip, configured to output a first reference voltage to a first output terminal;
• and
• a second reference voltage generating circuit configured to output a second reference voltage to a second output terminal, wherein the second reference voltage generating circuit includes:
• at least one pull-up resistor coupled between a first node and the second output terminal, wherein the first node is electrically coupled to an external power supply voltage of the chip;
• at least one first pull-down resistor disposed outside the chip and coupled to the second output terminal;
• a second pull-down resistor disposed in the chip and coupled to a ground;
• and
• a conductive line having a first impedance configured to be electrically coupled between the at least one first pull-down resistor and the second pull-down resistor, wherein a third reference voltage is outputted at a node where the first output terminal is electrically shorted to the second output terminal.

A method of generating a reference voltage, comprising:

• outputting a first reference voltage that is generated outside a chip to a first output terminal;
• pulling up a second reference voltage to a voltage at the first node, wherein the first node is electrically coupled to a power supply voltage of the chip;
• pulling down the second reference voltage to a voltage at a second node, wherein the voltage at the second node is relatively lower than the voltage at the first node;
• outputting the second reference voltage to a second output terminal;
• and
• outputting a third reference voltage of a node where the first output terminal is electrically shorted to the second output terminal.