Integrated circuit with increased heat transfer

An integrated circuit die comprising:

• circuit elements formed closer to a first surface of a semiconductor substrate than to a second surface of the semiconductor substrate;
• the semiconductor substrate having a varying profile, the varying profile substantially increasing the surface area of a thermal interface formed on the second surface as compared to the second surface being substantially planar;
• a thermally conductive layer thermally coupled to the semiconductor substrate, the thermally conductive layer being electrically isolated from the circuit elements;
• and
• wherein the thermally conductive layer interfaces a dielectric layer formed between the first surface of the semiconductor substrate and the circuit elements.

A method comprising:

• reducing a thermal resistivity of an integrated circuit die by increasing the surface area of a first surface of a semiconductor substrate, circuit elements being formed closer to a second surface of the semiconductor substrate than to the first surface;
• reducing the thermal resistivity of the die by thermal dissipation via a thermally conductive layer formed on the first side of the die;
• and
• wherein the thermally conductive layer is electrically isolated from the circuit elements and interfaces a dielectric layer formed between the second surface of the semiconductor substrate and the circuit elements.

An apparatus comprising:

• means for reducing a thermal resistivity of an integrated circuit die by increasing the surface area of a first surface of a semiconductor substrate, circuit elements being formed closer to a second surface of the semiconductor substrate than to the first surface;
• means for reducing the thermal resistivity of the die by thermal dissipation via a thermally conductive layer formed on the first side of the die;
• means for electrically isolating the thermally conductive layer from the circuit elements;
• and
• means for interfacing a dielectric layer formed between the second surface of the semiconductor substrate and the circuit elements.