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US 2006/0038271 A1Published application
Substrate isolation design
AssigneeUnited Microelectronics Corp.
InventorTsun-Lai Hsu
Life of this patent
Estimating the term…
Abstract
A substrate isolation design includes a P substrate, a P well positioned on the P substrate, at least a device positioned in the P well, and at least a P substrate guard ring surrounding the device. A P+ guard ring, an N well guard ring, or a deep N well guard ring can be selectively interposed between the P substrate guard ring and the device to facilitate blocking substrate coupling effect.
Claims22
A substrate isolation design, comprising:
- a P substrate;
- a P well positioned on the substrate;
- at least a device positioned in the P well;
- at least a P substrate guard ring surrounding the device;
- and wherein
- an N well guard ring positioned between the device and the P substrate guard ring,
- wherein the P substrate guard ring is positioned beneath a shallow is isolation trench formed within the P well.
4 more elements
(canceled)
A substrate isolation design, comprising:
- a substrate;
- at least a device positioned on the substrate;
- a first guard ring surrounding the device;
- a second guard ring surrounding the first guard ring;
- and
- a third guard ring surrounding the second guard ring, the third guard ring being a substrate guard ring, wherein the second guard ring comprises an N well guard ring and the substrate guard ring is positioned beneath a shallow isolation trench.
3 more elements
(canceled)
(canceled)
A substrate isolation design, comprising:
- a P substrate;
- at least a device positioned in the substrate;
- at least a P substrate guard ring surrounding the device and an N well guard ring positioned between the device and the P substrate guard ring,
- wherein the P substrate guard ring is positioned beneath a shallow isolation trench.
1 more element
(canceled)
(canceled)
Dependencies are inferred from the claim text.