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US 2006/0038263 A1Published application
Semiconductor chip arrangement
AssigneeInfineon Technologies AG
InventorsMarkus Eigner, Wolfgang Gruber, Manfred Roth, Stefan Ruping
Life of this patent
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Abstract
A patterned connection plane between two semiconductor chips which are connected using face-to-face technology is patterned into first pads, second pads, and conductor strips which are alternatively connected to one of these pads. The conductor strips are connected to a read-out circuit in one of the semiconductor chips via connections.
Claims7
A semiconductor chip arrangement with ROM, comprising:
- first and second semiconductor chips arranged on top of one another and electrically conductively connected to one another such that they are permanently fastened to one another;
- and
- a patterned connection plane having an arrangement of contact areas provided in a form of a memory cell array, wherein the first and second semiconductor chips are permanently fastened to common connection contact areas in the patterned connection plane, and a respective memory cell is programmed by means of a respective one of two intended forms of the contact areas,
- wherein electrical connections of the contact areas to a read-out circuit present in at least one of the semiconductor chips are provided for applying an electrical potential and reading a respective memory cell.
1 more element
A semiconductor chip arrangement, comprising:
- face-to-face semiconductor chips;
- a connection plane, which is formed in a memory cell array and is connected between the semiconductor chips, wherein the connection plane is a ROM;
- and
- a read-out circuit, which is located in at least one of the semiconductor chips, for reading a respective memory cell.
1 more element
A semiconductor chip arrangement, comprising:
- face-to-face semiconductor chips;
- and
- a patterned connection plane, which connects the semiconductor chips and is patterned into first pads, second pads, and conductor strips which are alternatively connected to one of the first and second pads,
- wherein the conductor strips are connected to a read-out circuit located in one of the semiconductor chips.
1 more element
Dependencies are inferred from the claim text.