Transistor and method of manufacturing the same

A transistor comprising:

• a semiconductor substrate having a first surface of a {100} crystal plane, two second faces of the {100} crystal plane having heights lower than that of the first surface, and two side faces of a {111} crystal plane connecting the first surface to the second surface faces;
• a gate pattern formed on the first surface;
• two epitaxial layers formed on the second faces and the side faces, respectively;
• and
• two impurity regions respectively formed in the epitaxial layers.

A method of manufacturing a transistor comprising:

• providing a semiconductor substrate having a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a side face of a {111} crystal plane connecting the first surface to the second surface;
• forming a gate structure on the first surface;
• growing an epitaxial layer on the second surface and the side face;
• and
• implanting impurities into the epitaxial layer to form impurity regions.

A method of manufacturing a transistor comprising:

• forming a gate pattern on a surface of a {100} crystal plane of a semiconductor substrate;
• forming a first spacer on a sidewall of the gate pattern;
• forming a second spacer on the first spacer;
• etching portions of the semiconductor substrate adjacent to both sides of the gate pattern to form a recess including a bottom face of the {100} crystal plane having a height lower than that of the surface, and a side face of the {111} crystal plane connecting the surface to the bottom face, the recess exposing a portion of the gate pattern, the first spacer and the second spacer;
• growing an epitaxial layer in the recess;
• and
• implanting impurities into the epitaxial layer to form impurity regions.

A method of manufacturing a transistor comprising:

• forming a gate pattern on a surface of a {100} crystal plane of a semiconductor substrate;
• forming first spacers on sidewalls of the gate pattern;
• partially etching portions of the semiconductor substrate adjacent to the sidewalls of the gate pattern to form recesses including bottom faces of the {100} crystal plane having height lower than that of the surface, and a side faces of the {111} crystal plane connecting the surface to the bottom faces, the recesses exposing a portion of the gate pattern and the first spacers;
• growing epitaxial layers in the recesses, respectively;
• forming second spacers on the first spacers and the epitaxial layers;
• and
• implanting impurities into the epitaxial layers to form impurity regions.