Semiconductor device and manufacturing method of the same
AssigneeFujitsu Limited
InventorsTomohiko Tsutsumi, Toru Anezaki, Hideyuki Kojima, Taiji Ema
Life of this patent
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Abstract
An n-type embedded layer is formed in an N-LV region of a SRAM cell region after an element isolation insulating film is formed on a p-type Si substrate. Thereafter, a p-well and an n-well are formed. In formation of a channel-doped layer, ion implantation is also performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-LV of a logic circuit region. Ion-implantation is further performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-MV of an I/O region.
Claims19
A semiconductor device, comprising:
- a semiconductor substrate;
- a first transistor for a memory with a channel of a first conductivity type, formed on a surface of said semiconductor substrate;
- a first transistor for a peripheral circuit with a channel of the first conductivity type, formed on the surface of said semiconductor substrate;
- and
- a second transistor for the peripheral circuit with a channel of the first conductivity type, formed on the surface of said semiconductor substrate, an impurity profile of the channel of said first transistor for the memory being a total of that of said first transistor for the peripheral circuit and that of said second transistor for the peripheral circuit.
A semiconductor device, comprising:
- a semiconductor substrate of a first conductivity type;
- a first well of the first conductivity type formed on a surface of said semiconductor substrate;
- a second well of a second conductivity type formed on the surface of said semiconductor substrate;
- a first transistor for a memory with a channel of the first conductivity type, formed in said first well;
- a second transistor for the memory with a channel of the second conductivity type, formed in said second well;
- and
- an embedded well of the second conductivity type formed directly under said first well.
A manufacturing method of a semiconductor device, comprising the step of forming a first transistor for a memory with a channel of a first conductivity type, a first transistor for a peripheral circuit with a channel of the first conductivity type and a second transistor for the peripheral circuit with a channel of the first conductivity type, on a surface of a semiconductor substrate,
- an impurity profile of the channel of the first transistor for the memory being made a total of that of the first transistor for the peripheral circuit and that of the second transistor for the peripheral circuit.
A manufacturing method of a semiconductor device, comprising the steps of:
- forming an embedded well of a second conductivity type inside a semiconductor substrate of a first conductivity type;
- forming a first well of the first conductivity type on the embedded well on the surface of the semiconductor substrate;
- forming a second well of the second conductivity type at a position spaced from the first well on the surface of the semiconductor substrate;
- and
- forming a first transistor for a memory with a channel of the first conductivity type in the first well, and forming a second transistor for the memory with a channel of the second conductivity type in the second well.
Dependencies are inferred from the claim text.