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US 2006/0038210 A1Published application
Multi-sensing level MRAM structures
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWen Chin Lin, Denny Tang, Chien-Chung Hung
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Abstract
The present disclosure provides an improved magnetic memory cell. The magnetic memory cell includes a switching element and two magnetic tunnel junction (MTJ) devices. A conductor connects the first and second MTJ devices in a parallel configuration, and serially connecting the parallel configuration to an electrode of the switching element. The resistance of the first MTJ device is different from the resistance of the second.
Claims19
A magnetic memory cell comprising:
- a switching element;
- a first magnetic tunnel junction (MTJ) device having a first resistance;
- a second MTJ device having a second resistance;
- and
- a conductor for connecting the first and second MTJ devices in a parallel configuration and for serially connecting the parallel configuration of the first and second MTJ devices to an electrode of the switching element;
- wherein the first resistance is different from the second resistance.
3 more elements
A magnetic memory cell comprising:
- first, second, and third terminals;
- a conductor;
- a CMOS transistor having source, drain, and gate electrodes, the gate electrode connected to the third terminal, one of either the source or drain connected to the second terminal, and the other of either the source or drain connected to the conductor;
- a first magnetic tunnel junction (MTJ) device including a serially connected first free layer, first tunneling barrier, and first pinned layer, the first free layer also being connected to the first terminal and the first pinned layer also being connected to the conductor;
- and
- a second MTJ device including a serially connected second free layer, second tunneling barrier, and second pinned layer, the second free layer also being connected to the first terminal and the second pinned layer also being connected to the conductor;
- wherein a first resistance between the first terminal to the second terminal through the first MTJ device is different from a second resistance between the first terminal to the second terminal through the second MTJ device.
4 more elements
An integrated circuit comprising:
- a plurality of bit lines, word lines, and program lines;
- a plurality of magnetic memory cells, each including:
- a conductor;
- a transistor having source, drain, and gate electrodes, the gate electrode connected to one of the word lines, one of either the source or drain connected to a first program line, and the other of either the source or drain connected to the conductor;
- a first magnetic tunnel junction (MTJ) device including a serially connected first free layer, first tunneling barrier, and first pinned layer, the first free layer also being connected to a first bit line and the first pinned layer also being connected to the conductor;
- and
- a second MTJ device including a serially connected second free layer, second tunneling barrier, and second pinned layer, the second free layer also being connected to the first bit line and the second pinned layer also being connected to the conductor;
- wherein a first resistance between the first bitline to the conductor through the first MTJ device is different from a second resistance between the first bitline to the conductor through the second MTJ device.
5 more elements
Dependencies are inferred from the claim text.