Stacked packages

A method of making semiconductor chip assembly comprising the steps of:

• (a) stacking a plurality of units each including at least one semiconductor chip having at least one chip select contact and a plurality of other contacts and a circuit panel having a plurality of chip select terminals, a plurality of other terminals, and traces extending on or in the panel connected to said terminals, said traces of each panel including a plurality of traces connecting said other contacts with said other terminals, at least one trace of each said panel being a multi-branched trace associated with plurality of said chip select terminals on such panel, each such multi-branched trace including a common section and a plurality of branches, each one of the plurality of branches being associated with one said chip select terminals, each one of said branches defining a gap intervening between the common section of the trace incorporating such branch and the terminal associated with such branch;
• (b) selectively connecting a bridging conductive element across the gap defined by at least one branch, but less than all branches, of each such multi-branched trace, whereby the common section of each multi-branched trace is connected to less than all of the chip select terminals associated with the branches of such multi-branched trace;
• and
• (c) interconnecting terminals of different units to one another to form vertical buses, said selectively connecting and interconnecting steps being performed so that the chip select contacts of chips in different units are connected to different ones of said vertical buses.