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US 2006/0033170 A1Published application
Transistor arrangement
AssigneeInfineon Technologies AG
InventorRalf Brederlow
Life of this patent
Estimating the term…
Abstract
A transistor arrangement having a multiplicity of transistors interconnected with one another, having a noise detection device, which is set up for detecting the 1/f noise of at least one portion of the transistors, having a selection device, which is set up for selecting at least one of the transistors, on the basis of the ascertained 1/f noise characteristic of the transistors, in the case of which the 1/f noise is sufficiently low.
Claims31
1-15. (canceled)
A transistor arrangement comprising:
- a plurality of transistors interconnected with one another;
- a noise detection device for detecting the intensity of the 1/f noise of at least one portion of the transistors;
- and
- a selection device for selecting at least one of the transistors based on the detected 1/f noise of the transistors, when the 1/f noise is sufficiently low.
1 more element
A transistor arrangement comprising:
- a plurality of transistors interconnected with one another;
- a noise detection means for detecting the intensity of the 1/f noise of at least one portion of the transistors;
- and
- a selection means for selecting at least one of the transistors based on the detected 1/f noise of the transistors, when the 1/f noise is sufficiently low.
1 more element
Dependencies are inferred from the claim text.