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US 2006/0033149 A1Published application
Semiconductor device and method of manufacturing the same
AssigneeMacronix International Co., Ltd.
InventorsMu-Yi Liu, Tao-Cheng Lu
Life of this patent
Estimating the term…
Abstract
An EEPROM cell includes first and second assist gates on opposite sides of a charge retaining insulating layer. Current in the EEPROM memory cell flows between inversion layers, which are created in response to a bias applied to the assist gates. The insulating layer can include silicon nitride, which is provided between layers of silicon dioxide above the channel region, such that these layers can constitute a dielectric stack, which can be fabricated to occupy a relatively small area.
Claims23
A semiconductor device, comprising:
- a substrate;
- a first conductive layer provided on a first region of the substrate, and being insulated from the first region of the substrate;
- a second conductive layer provided on a second region of the substrate, the first region being spaced from the second region, the second conductive layer being insulated from the second region of the substrate;
- and
- an insulating layer provided on a third region of the substrate, the third region being between the first and second regions;
- and
- a third conductive layer provided on the insulating layer,
- wherein upon application of first, second, and third biases to the first, second, and third conductive layers, respectively, the insulating layer receives and retains the carriers.
5 more elements
A semiconductor device, comprising:
- a substrate;
- a dielectric stack provided on the substrate and configured to retain charge and including
- a first layer of silicon oxide,
- a second layer of silicon nitride, and
- a third layer of silicon oxide;
- a first polysilicon layer laterally spaced from the dielectric stack, the first polysilicon layer being insulated from the substrate;
- a second polysilicon layer laterally spaced from the dielectric stack and the first polysilicon layer, the second polysilicon layer being insulated from the substrate;
- and
- a third polysilicon layer provided on the third silicon dioxide layer, the first polysilicon layer and the second polysilicon layer, the third polysilicon layer being insulated from the first and second polysilicon layers.
6 more elements
A semiconductor device, comprising:
- a substrate having a surface;
- a first assist gate line being insulated from and extending over a first region of the surface of the substrate;
- a second assist gate line being insulated from and extending over a second region of the surface of the substrate, the first and second regions being spaced from one another;
- an insulating layer being provided on a third region of the surface of the substrate, the third region being between the first and second regions;
- and
- a word line on the insulating layer,
- wherein upon application of first, second, and third biases to the first assist gate line, the second assist gate line, and the word line, respectively, the insulating layer receives carriers, the insulating layer being configured to retain the carriers, and first and second inversion layers are formed adjacent to the first and second assist gate lines, respectively, in response to the first and second biases;
- and
- first and second doped regions provided in the substrate, the first and second doped regions being configured to bias the first and second inversion layers, respectively.
6 more elements
A method of fabricating a semiconductor device on a substrate surface, comprising:
- forming a first insulating layer on a first region of the substrate surface;
- forming a second insulating layer on the first insulating layer;
- forming a third insulating layer on the substrate and the second insulating layer;
- forming a first conductive layer, on the third insulating layer, laterally spaced from the first and second insulating layers;
- forming a second conductive layer, on the third insulating layer, laterally spaced from the first and second insulating layers;
- and
- forming a third conductive layer on the third insulating layer.
4 more elements
A method for fabricating a semiconductor device, comprising:
- forming a dielectric stack on a substrate, including
- a first layer of silicon oxide,
- a second layer of silicon nitride, and
- a third layer of silicon oxide;
- forming a first polysilicon layer laterally spaced from the dielectric stack;
- forming a second polysilicon layer laterally spaced from the dielectric stack;
- oxidizing portions of the first and second polysilicon layers;
- and
- forming a third polysilicon layer on the dielectric stack and the oxidized portions of the first and second polysilicon layers.
6 more elements
Dependencies are inferred from the claim text.