Integrated memory device and process
AssigneeInfineon Technologies AG
InventorsRonald Kakoschke, Thomas Nirschl, Danny Shum, Klaus Schrufer
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Abstract
A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions.
Claims19
A memory device comprising:
- a plurality of storage cells arranged in a matrix containing rows of storage cells and columns of storage cells, each storage cell containing at least one cell transistor, each cell transistor containing a first doped regions and a second doped regions, one of the first and second doped regions being a drain region and the other of the first and second regions being a source region, the first doped regions of a different doping type than the second doped regions;
- a plurality of word lines, each word line connected to storage cells of one row;
- and
- a plurality of first bit lines, each first bit line connected to storage cells of one column.
A method of fabricating a memory device in a semiconductor substrate, the device having a memory array comprising a plurality of memory cell transistors arranged in rows and columns, the method comprising:
- forming a plurality of word lines, each word line connected to storage cells of one row;
- forming first doped regions and second doped regions in each column, one of the first and second doped regions being a drain region and the other of the first and second doped regions being a source region, the first doped region having a first doping type and the second doping region having a second doping type different from the first doping type;
- and
- forming a plurality of first bit lines, each first bit line connected to storage cells of one column.
Dependencies are inferred from the claim text.