Non-planar flash memory array with shielded floating gates on silicon mesas
AssigneeMicron Technology, Inc.
InventorsLeonard Forbes, Kie Ahn
Life of this patent
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Abstract
A first plane of memory cells is formed on mesas of the array. A second plane of memory cells is formed in valleys adjacent to the mesas. The second plurality of memory cells is coupled to the first plurality of memory cells through a series connection of their source/drain regions. Wordlines couple rows of memory cells of the array. Metal shields are formed between adjacent wordlines and substantially parallel to the wordlines to shield the floating gates of adjacent cells.
Claims44
A non-planar flash memory array with shielded memory cells arranged in rows and columns, each memory cell comprising a floating gate and a control gate coupled to a wordline, the array comprising:
- a first plurality of memory cells each formed on a silicon mesa on a substrate;
- a second plurality of memory cells each formed in a valley between silicon mesas;
- and
- metal shielding formed between adjacent wordlines.
A flash memory array comprising:
- a plurality of flash memory cells each comprising a floating gate and arranged in a matrix of rows and columns on a substrate, each row of memory cells coupled by a wordline and fabricated on a plurality of planes;
- and
- a metal shield material formed between adjacent wordlines such that the floating gates of memory cells in the adjacent rows are shielded.
A flash memory device comprising:
- a plurality of columns of memory cells, the memory cells of each column fabricated in multiple planes of a substrate;
- a plurality of rows of memory cells, each row of memory cells fabricated in the multiple planes, the memory cells of each row coupled through a wordline;
- and
- a metal layer formed between adjacent wordlines and substantially parallel to the wordlines.
A method for fabricating a non-planar flash memory array, with shielded floating gates, comprising a plurality of memory cells, the method comprising:
- forming a mesa/valley structure, comprising a plurality of mesas and valleys, in a substrate;
- forming source/drain regions in sidewalls of the mesas;
- forming a gate insulator layer over the substrate;
- depositing a first polysilicon layer;
- etching the polysilicon to form floating gates in the valleys and on the mesas;
- forming an intergate insulator layer over the floating gates;
- forming a second polysilicon layer over the intergate insulator to produce wordlines;
- and
- forming a metal layer on between and substantially parallel to the wordlines to shield the floating gates.
A method for fabricating a non-planar flash memory array comprising a plurality of memory cells with shielded floating gates, the method comprising:
- directionally etching a substrate to form a plurality of mesas and valleys;
- forming source/drain regions in sidewalls of the first trenches;
- forming a gate insulator layer over the substrate;
- depositing a floating gate layer;
- etching the floating gate layer to form floating gates in the first trenches and on the pillars;
- etching second trenches in the substrate in a direction that is substantially perpendicular to the first trenches, the second trenches having a second depth in the substrate that is greater than the first depth;
- forming an intergate insulator layer over the floating gates;
- forming a wordline over the intergate insulator to connect memory cells in each row of the array such that the wordline extends down into the second trenches to shield floating gates in the first trenches from adjacent floating gates across the second trenches and to shield floating gates on pillars from adjacent floating gates on pillars across the second trenches;
- forming a metal shield along the first trenches to shield floating gates on pillars from adjacent floating gates on pillars across the first trenches;
- and
- performing a metallization process for contacts.
A method for programming a non-planar flash memory array, with shielded floating gates, comprising rows and columns of flash memory cells, each row of memory cells coupled on a first and a second plane by a wordline and each column of memory cells coupled on the first and the second plane, each memory cell having a pair of source/drain regions, a gate insulator, a floating gate, and a control gate, a metal shield layer extending between adjacent wordlines on different planes, the method comprising:
- biasing the control gate with a first positive voltage;
- biasing a first source/drain region with a second positive voltage;
- and
- grounding the remaining source/drain region to create a hot electron injection into a gate insulator of the floating gate.
A method for programming a non-planar flash memory array, with shielded floating gates, comprising rows and columns of flash memory cells, each row of memory cells coupled on a first and a second plane by a wordline and each column of memory cells coupled on the first and the second plane, each memory cell having a pair of source/drain regions, a gate insulator, a floating gate, and a control gate, a metal shield layer extending between adjacent wordlines on different planes, the method comprising:
- biasing the control gate;
- allowing a first source/drain region to float;
- and
- biasing the remaining source/drain region with a positive voltage.
An electronic system comprising:
- a processor that generates memory control signals;
- and
- a non-planar, flash memory device coupled to the processor, the device comprising:
- a plurality of columns of memory cells, the memory cells of each column fabricated in multiple planes of a substrate;
- a plurality of rows of memory cells, each row of memory cells fabricated in the multiple planes, the memory cells of each row coupled through a wordline;
- and
- a metal layer formed between adjacent wordlines and substantially parallel to the wordlines such that adjacent memory cells are shielded.
Dependencies are inferred from the claim text.