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US 2006/0033128 A1Published application
Logic switch and circuits utilizing the switch
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorMin-Hwa Chi
Life of this patent
Estimating the term…
Abstract
A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic switch is unidirectionally conductive. A third voltage renders the logic switch bidirectionally non-conductive. Circuits containing the logic switch are also described. These circuits include inverters, SRAM cells, voltage reference sources, and neuron logic switches. The logic switch is primarily implemented according to SOI protocols, but embodiments according to bulk protocols are described.
Claims57
A logic switch, comprising:
- a first semiconductor region of a first conductivity type;
- a second semiconductor region of a second conductivity type adjacent to the first semiconductor region so that a pn junction is defined between the regions;
- and
- a gate overlying the pn junction and the immediate junction-adjacent surfaces of the regions, the gate including
- a thin oxide layer on the surface of the regions, and
- a conductive gate electrode on the thin oxide layer, the electrode being sufficiently doped with a dopant of the first conductivity type to place the surface of said second region under the gate in majority carrier depletion and the surface of said first region under the gate in majority carrier accumulation, such conditions being, at thermal equilibrium and with there being no potential difference between the gate electrode and the regions, conducive to the flow of gate-induced drain leakage (GIDL) current between the regions.
3 more elements
An inverter comprising:
- a first logic switch including
- a first semiconductor layer of a first conductivity type;
- a first region of a second conductivity type formed in a second region of the first semiconductor layer, a first junction being defined between the first and second regions;
- and
- a first gate overlying the first junction and the immediate first-junction-adjacent surfaces of the first and second regions, the first gate including
- a first thin oxide layer on the surface of the first and second regions, and
- a first gate electrode on the first thin oxide layer, the first gate electrode being sufficiently doped with a dopant of the first conductivity type to place the surface of the first region under the first gate in majority carrier depletion and the surface of the second region under the first gate in majority carrier accumulation, such conditions being conducive, at thermal equilibrium and with there being no potential difference between the first gate electrode and the first and second regions, to GIDL current flow between the regions;
- a second logic switch including
- a second semiconductor layer of the second conductivity type;
- a third region of the first conductivity type formed in a fourth region of the second layer, a second boundary being defined between the third and fourth regions;
- and
- a second gate overlying the second boundary and the immediate second-junction-adjacent surfaces of the third and fourth regions, the second gate including
- a second thin oxide layer on the surface of the third and fourth regions, and
- a second gate electrode on the second thin oxide layer, the second gate electrode being sufficiently doped with a dopant of the second conductivity type to place the surface of the third region under the second gate in majority carrier depletion and the surface of the fourth region under the second gate in majority carrier accumulation, such conditions being conducive, at thermal equilibrium and with there being no potential difference between the second gate electrode and the third and fourth regions, to GIDL current flow between the regions;
- an electrical connection between the first and second gate electrodes for receiving an input voltage Vi;
- separate electrical connections to the first and third regions, respectively, for receiving biasing voltages;
- and
- an electrical connection between the first and third regions for producing an output voltage Vo in response to application of an input voltage.
15 more elements
A voltage reference, comprising:
- a pair of logic switches, each including
- a first semiconductor region of a first conductivity type,
- a second semiconductor region of a second conductivity type, a pn junction being defined between the regions,
- a gate overlying the pn junction and the immediate junction-adjacent surfaces of the regions, the gate including
- a thin oxide layer on the surface of the regions, and
- a conductive gate electrode on the thin oxide layer, the gate electrode of a first of the logic switches being doped with a dopant of the first conductivity type and the gate electrode of the second of the logic switches being doped with a dopant of the second conductivity type;
- an operational amplifier having
- its output Vo connected to the gate electrode of the first logic switch,
- its inverting input connected to the first region of the first logic switch, and
- its non-inverting input connected to the first region of the second logic switch;
- a ground connection to the gate electrode of the second logic switch;
- and
- facilities for reverse biasing the logic switches.
10 more elements
A logic switch, comprising:
- a first region of a first conductivity type and an adjacent second region of a second conductivity type, the regions defining a pn junction therebetween;
- a gate electrode overlying the pn junction and the immediate junction-neighboring areas of the regions, the gate electrode being separated from the pn junction by an insulating medium;
- and
- a connection to each region adapted to permit the application of selected input voltages to the gate electrode;
- the regions, the gate electrode, and the insulating medium being so constituted that
- a first input voltage is capable of initiating GIDL current flow between the regions and current can flow bi-directionally between the connections,
- a second voltage terminates GIDL current flow but forward biases the pn junction so that current may flow uni-directionally between the connections, and
- a third voltage bi-directionally prevents current flow between the connections.
5 more elements
A neuron logic switch, comprising:
- a semiconductor layer of a first conductivity type;
- a first region of a second conductivity type formed in a second region of the semiconductor layer;
- a boundary being defined between the regions;
- and
- a gate overlying the boundary and the immediately adjacent surfaces of the regions, the gate including
- a thin oxide layer on the surface of the regions;
- a conductive gate electrode on the thin oxide layer, the electrode being sufficiently doped with a dopant of the first conductivity type to place the surface of first region under the gate in majority carrier depletion and the surface of the second region under the gate in majority carrier accumulation, such conditions being conducive, at thermal equilibrium and with there being no potential difference between gate electrode and the regions, to GIDL current flow between the regions;
- a conductive member that is electrically continuous with the gate electrode and remote from the boundary;
- and
- two or more input electrodes for receiving input voltages, the input electrodes overlying the conductive member, each input electrode having an area capacitively coupled to a congruent area of the conductive member so that the voltage on the gate electrode is the weighted sum of voltages applied to the input electrodes.
7 more elements
An SOI logic switch, comprising:
- a first oxide layer on a substrate;
- a layer of a first conductivity type semiconductor on the oxide layer;
- a diode site defined in an enclosed volume of the semiconductor layer between a free surface thereof and the first oxide layer, the enclosed volume being electrically isolated from the remainder of the semiconductor layer;
- a first region of a second conductivity type formed in a portion of the enclosed volume, the remainder of which is a second adjacent region of the first conductivity type;
- and
- a gate overlying the boundary between the regions, the gate including
- a second, thin oxide layer on the semiconductor layer, and
- a conductive gate electrode on the second, thin oxide layer, the electrode being doped with a dopant of the first conductivity type.
5 more elements
An SOI logic switch, comprising:
- a first oxide layer on a substrate;
- a layer of n-type semiconductor on the oxide layer;
- a diode site defined in an enclosed volume of the semiconductor layer between a free surface thereof and the oxide layer, the enclosed volume being electrically isolated from the remainder of the semiconductor layer;
- a p+ region formed in a portion of the enclosed volume, the remainder of which is an adjacent n-region;
- a second, thin oxide layer on the semiconductor layer, the thin oxide layer overlying the boundary between the regions;
- and
- an n-doped conductive gate electrode on the thin oxide layer.
4 more elements
The logic switch of claim 49, wherein a potential difference of the second polarity sufficiently greater than the selected magnitude effects full depletion of the second region under the gate, thereby rendering current incapable of flowing between the regions.
An SOI logic switch, comprising:
- a first oxide layer on a substrate;
- a layer of p-type semiconductor on the oxide layer;
- a diode site defined in an enclosed volume of the semiconductor layer between a free surface thereof and the oxide layer, the enclosed volume being electrically isolated from the remainder of the semiconductor layer;
- a n+ region formed in a portion of the enclosed volume, the remainder of which is an adjacent p-region;
- a second, thin oxide layer on the semiconductor layer, the thin oxide layer overlying the boundary between the regions;
- and
- a p-doped conductive gate electrode on the thin oxide layer.
4 more elements
A logic switch, comprising:
- a substrate of a first conductivity type;
- a well of a second conductivity type formed in the substrate;
- a region of the first conductivity type formed within a portion of the well to create a boundary with the well, the boundary and the adjacent areas of the well and the region being a diode site;
- and
- a gate overlying the boundary, the gate including
- a thin oxide layer, and
- a conductive gate electrode on the oxide layer, the electrode being doped with a dopant of the first conductivity type.
4 more elements
Dependencies are inferred from the claim text.