Highly parallel structure for fast multi cycle binary and decimal adder unit
AssigneeInternational Business Machines Corporation
InventorsWilhelm Haller, Wen Li, Michael Kelly, Holger Wetter
Life of this patent
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Abstract
An adder circuit for adding two binary or two decimal operands A and B in which the carries are calculated directly from the input operands A and B without including the plus 6 or minus 6 operations into the carry calculation. For all timing critical functions the reduced input data set, i.e., valid decimal data can be used and the non-existing decimal numbers (10 to 15) need not be excluded by separate check logic any more. This reduces the complexity of the logic functions.
Claims15
An adder circuit for adding either binary or decimal operands, the operands comprising a first operand to a second operand, the first operand comprising a plurality N of 4 bit digits A, a first operand digit represented by A(N-1), the second operand comprising the plurality N of 4 bit digits B, a second operand digit represented by B(N-1), the adder circuit comprising:
- a) a first decimal digit sum calculator adapted to calculate digit sums, the digit sums for each digit of the plurality of N digits, the first decimal digit sum calculations comprising:
- A(N-1) plus B(N-1) plus 6,
- A(N-1) minus B(N-1) minus 6,
- A(N-1) plus B(N-1), and
- A(N-1) minus B(N-1);
- b) a second decimal digit sum calculator adapted to calculate digit sums, the digit sums for each digit of the plurality of N digits, the second decimal digit sum calculations comprising:
- A(N-1) plus B(N-1) plus 6 plus 1,
- A(N-1) minus B(N-1) minus 6 plus 1,
- A(N-1) plus B(N-1) plus 1, and
- A(N-1) minus B(N-1) plus 1;
- c) a carry subcircuit generating “hot” carries into digits of the plurality of N digits;
- d) a pre-sum circuit for calculating a carry-out cy0-cyN directly from the plurality of digits of the first and second operands;
- and
- e) a final sum circuit generating final digit sums of the plurality of digits by selecting digit sums of the digit calculator based on respective digit carry-out of the pre-sum circuit and respective “hot” carries of the carry subcircuit.
An adder circuit method for adding either binary or decimal operands, the operands comprising a first operand to a second operand, the first operand comprising a plurality N of 4 bit digits A, a first operand digit represented by A(N-1), the second operand comprising the plurality N of 4 bit digits B, a second operand digit represented by B(N-1), the method comprising:
- a) a first decimal digit sum calculator calculating digit sums, the digit sums for each digit of the plurality of N digits, the first decimal digit sum calculations comprising:
- A(N-1) plus B(N-1) plus 6,
- A(N-1) minus B(N-1) minus 6,
- A(N-1) plus B(N-1), and
- A(N-1) minus B(N-1);
- b) a second decimal digit sum calculator calculating digit sums, the digit sums for each digit of the plurality of N digits, the second decimal digit sum calculations comprising:
- A(N-1) plus B(N-1) plus 6 plus 1,
- A(N-1) minus B(N-1) minus 6 plus 1,
- A(N-1) plus B(N-1) plus 1, and
- A(N-1) minus B(N-1) plus 1;
- c) a carry subcircuit generating “hot” carries into digits of the plurality of N digits;
- d) a pre-sum circuit calculating a carry-out cy0-cyN directly from the plurality of digits of the first and second operands;
- and
- e) a final sum circuit generating final digit sums of the plurality of digits by selecting digit sums of the digit calculator based on respective digit carry-out of the pre-sum circuit and respective “hot” carries of the carry subcircuit
An adder circuit for adding two binary or decimal operands A and B, wherein in case of decimal operands each decimal digit 0 to 9 has a binary 4-bit representation, and wherein decimal-digitwise operations are performed including a digit sum calculation of:
- operand A plus operand B plus 6,
- operand A minus operand B minus 6,
- operand A plus operand B,
- operand A minus operand B,
- wherein the carry-out of a decimal digit is indicating if or if not a correction to the digit sum is required, said adder circuit comprising:
- a) a first carry subcircuit for generating “hot” carries into each digit,
- b) a second adder subcircuit for precalculating all possible digit sums A plus B, A minus B, and A plus B plus 6, and A minus 6 minus B for decimal operands, respectively, for both, assumed carry-in values of 0 and 1, characterized by
- c) a pre-sum logic for calculating the carry-out cy0, cy1, cy2 and cy3 directly from the input operands,
- d) said pre-sum logic implementing the following formula or a logical equivalent thereof:
- Cy0=g0+(g1*p0)+(g2*p0*p1)+(g3*p0*p1*p2)
- Cy1=g0+(g1*p0)+(g2*p0*p1)+(p0*p1*p2*p3)
- Cy2=g0+(p0*p1)+(p0*p2)+(p0*g3)+(g1*p2)+(g1*g3)+(p1*g2*g3)
- Cy3=g0+(p0*p1)+(p0*p2)+(p0*p3)+(g1*p2)+(g1*p3)+(p1*g2*p3)
- wherein:
- * represents a logical <AND>,
- + represents a locical <OR>,
- g(n)=A(n) <AND> B(n), and
- p(n)=A(n) <OR> B(n).
Dependencies are inferred from the claim text.