US 2006/0008982 A1Published application

Method of recording information in nonvolatile semiconductor memory

AssigneeOki Electric Industry Co., Ltd.

InventorTakashi Ono

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Abstract

In one example, a nonvolatile semiconductor memory includes a transistor, one or two resistance-change portions, and one or two charge accumulation portions. The transistor has a control electrode, first main electrode region, and second main electrode region. If two resistance-change portions are provided, one of them is provided in the surface region of a substrate between the first main electrode region and a channel formation region opposing the control electrode, and the other is provided in the surface region of the substrate between the second main electrode region and the channel formation region. Each resistance-change portion is of a second conductivity type having impurity concentration lower than that of the first and second main electrode regions. The charge accumulation portions are provided on the associated resistance-change portions. Each charge accumulation portion has an insulating layer, and is capable of accumulating charge. It should be assumed that information is recorded in such nonvolatile semiconductor memory in which information has been erased in advance by charge accumulation. When the first conductivity type is the p type and the second conductivity type is the n type, an information recording method includes applying a high positive voltage to one of the main electrode regions, setting the other main electrode region to ground voltage, and applying a positive voltage to the control electrode so as to cause weak inversion of the channel formation region.

Claims18

Dependent claims

A method of recording information in a nonvolatile semiconductor memory, after erasing information in the nonvolatile semiconductor memory by charge accumulation, said nonvolatile semiconductor memory including:

a substrate of a first conductivity type;
a transistor having a control electrode provided on said substrate with a first insulating film intervening, and a first main electrode region and second main electrode region which are a pair of diffusion regions provided in a surface region of the substrate, with impurities of a second conductivity type differing from said first conductivity type, said control electrode being located between said first and second main electrode regions;
a channel formation region formed in said substrate and opposing said control electrode over the first insulating film;
a first resistance-change portion of said second conductivity type, provided in the surface region of said substrate between one of said first and second main electrode regions and said channel formation region, an impurity concentration of said first resistance-change portion being lower than that of said one of first and second main electrode regions;
and,
a first charge accumulation portion provided on the first resistance-change portion, the first charge accumulation portion having a first insulating layer and capable of accumulation of charge;
wherein
when said first conductivity type is a p type and said second conductivity type is an n type, said method comprises:
applying a high positive voltage to said one of said first and second main electrode regions;
setting the other of said first and second main electrode regions to ground voltage;
and,
applying a positive voltage to said control electrode to cause weak inversion of said channel formation region;
and,
when said first conductivity type is the n type and said second conductivity type is the p type, said method comprises:
applying a high negative voltage to said one of said first and second main electrode regions;
setting the other of said first and second main electrode regions to the ground voltage;
and,
applying a negative voltage to said control electrode to cause the weak inversion of said channel formation region.

15 more elements

A method of recording information in a nonvolatile semiconductor memory, after information is erased in the nonvolatile semiconductor memory by charge accumulation, said nonvolatile semiconductor memory including:

a substrate of a first conductivity type;
a transistor having a control electrode provided on said substrate with a first insulating film intervening, and a first main electrode region and second main electrode region which are a pair of diffusion regions with impurities of a second conductivity type differing from said first conductivity type, the first and second main electrode regions being provided in the surface region of said substrate, said control electrode being located between said first and second main electrode regions;
a channel formation region formed in said substrate and opposing said control electrode over the first insulating film;
a first resistance-change portion of said second conductivity type, provided in the surface region of said substrate between one of said first and second main electrode regions and said channel formation region, with an impurity concentration of said first resistance-change portion being lower than that of said one of said first and second main electrode regions;
and,
a first charge accumulation portion provided on the first resistance-change portion, the first charge accumulation portion having a first insulating layer and capable of accumulation of charge;
wherein
when said first conductivity type is a p type and said second conductivity type is an n type, an amount of accumulation of charge in said first charge accumulation portion is controlled by repeating:
applying a high positive voltage to said one of said first and second main electrode regions, setting the other of said first and second main electrode regions to ground voltage, and applying a positive voltage to said control electrode, to neutralize charge;
and,
setting said one of said first and second main electrode regions to the ground voltage and applying a positive voltage to said the other of said first and second main electrode regions and to said control electrode, to read recorded information;
and,
when said first conductivity type is the n type and said second conductivity type is the p type, the amount of accumulation of charge in said first charge accumulation portion is controlled by repeating:
applying a high negative voltage to said one of said first and second main electrode regions, setting the other of said first and second main electrode regions to the ground voltage, and applying a negative voltage to said control electrode, to neutralize charge;
and,
setting said one of said first and second main electrode regions to the ground voltage and applying a negative voltage to said other of said first and second main electrode regions and to said control electrode, to read recorded information.

13 more elements

a substrate of a first conductivity type;
a transistor having a control electrode provided on said substrate with a first insulating film intervening, and a first main electrode region and second main electrode region which are a pair of diffusion regions provided in a surface region of said substrate, with impurities of a second conductivity type differing from said first conductivity type, said control electrode being located between said first and second main electrode regions;
a channel formation region formed in said substrate and opposing said control electrode over the first insulating film;
a first resistance-change portion of said second conductivity type, provided in the surface region of said substrate between said first main electrode region and said channel formation region, an impurity concentration of said first resistance-change portion being lower than that of said first main electrode region;
a first charge accumulation portion provided on the first resistance-change portion, the first charge accumulation portion having a first insulating layer and capable of accumulation of charge;
a second resistance-change portion of said second conductivity type, provided in the surface region of said substrate between said second main electrode region and said channel formation region, an impurity concentration of said second resistance-change portion being lower than that of said second main electrode region;
and,
a second charge accumulation portion provided on the second resistance-change portion, the second charge accumulation portion having a second insulating layer and capable of accumulation of charge;
wherein
when said first conductivity type is a p type and said second conductivity type is an n type, and information should be recorded in said first charge accumulation portion, said method comprises:
applying a high positive voltage to said first main electrode region;
setting said second main electrode region to ground voltage;
and,
applying a positive voltage to said control electrode to cause weak inversion of said channel formation region;
when said first conductivity type is a p type and said second conductivity type is an n type, and information should be recorded in said second charge accumulation portion, said method comprises:
applying a high positive voltage to said second main electrode region;
setting said first main electrode region to ground voltage;
and,
applying a positive voltage to said control electrode to cause weak inversion of said channel formation region;
when said first conductivity type is the n type and said second conductivity type is the p type, and information should be recorded in said first charge accumulation portion, then said method comprises:
applying a high negative voltage to said first main electrode region;
setting said second main electrode region to the ground voltage;
and,
applying a negative voltage to said control electrode to cause the weak inversion of said channel formation region;
and
when said first conductivity type is the n type and said second conductivity type is the p type, and information should be recorded in said second charge accumulation portion, then said method comprises:
applying a high negative voltage to said second main electrode region;
setting said first main electrode region to the ground voltage;
and,
applying a negative voltage to said control electrode to cause the weak inversion of said channel formation region.

27 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/060,297Filed 18 Feb 2005
Priority: JP 2004-2004687 Jul 2004
Published: 12 Jan 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G11C 16/0475
Comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]:…
G11C 11/5671
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using charge trapping in…
H10D 30/0413
Of FETs having insulated gates [IGFET]: of FETs having charge-trapping gate insulators, e.g. MNOS transistors
H10D 30/691
IGFETs having charge trapping gate insulators, e.g. MNOS transistors: having more than two programming levels