US 2005/0240791 A1 · Interleaved delay line for phase locked and delay locked loops

Abstract

An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

Claims47

Dependent claims

(canceled)

A memory device, comprising:

a plurality of memory cells;
and
a plurality of peripheral devices for reading information from said plurality of memory cells, said plurality of peripheral devices comprising a dual locked loop, comprising:
a first locked loop for establishing a phase relationship between an output signal and a reference signal;
a second locked loop responsive to said first locked loop and comprising:
a delay line having a first portion having a plurality of taps for providing a variable amount of load adjustment and a second portion in series with said first portion, said second portion having a plurality of taps for providing a variable amount of drive adjustment;
a control circuit for controlling the amount of load adjustment and drive adjustment such that a tuning range of said delay line is equal to (M/2)(tdl+tdp) where M is the number of taps, tdl is a range of delay provided by said first portion and tdp is a range of delay provided by said second portion;
a phase detector for producing signals for input to said control circuit;
and
a feedback path for connecting an output of said delay line to an input of said first locked loop and to said phase detector, said output signal being available at said output of said delay line.

7 more elements

A system, comprising:

a processor;
a memory device;
and
a bus for interconnecting said processor and said memory device, said memory device comprising a plurality of memory cells and a plurality of peripheral devices for reading information from said plurality of memory cells, said plurality of peripheral devices comprising a dual locked loop, comprising:
a first locked loop for establishing a phase relationship between an output signal and a reference signal;
a second locked loop responsive to said first locked loop and comprising:
a delay line having a first portion having a plurality of taps for providing a variable amount of load adjustment and a second portion in series with said first portion, said second portion having a plurality of taps for providing a variable amount of drive adjustment;
a control circuit for controlling the amount of load adjustment and drive adjustment such that a tuning range of said delay line is equal to (M/2)(tdl+tdp) where M is the number of taps, tdl is a range of delay provided by said first portion and tdp is a range of delay provided by said second portion;
a phase detector for producing signals for input to said control circuit;
and
a feedback path for connecting an output of said delay line to an input of said first locked loop and to said phase detector, said output signal being available at said output of said delay line.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/080,678Filed 14 Mar 2005

Priority

31 Aug 2000

Published

27 Oct 2005

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 1/10
Generating or distributing clock signals or signals derived directly therefrom: distribution of clock signals , e.g. skew
G11C 7/1072
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: for memories with random access ports…
G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
H03L 7/0814
And where no voltage or current controlled oscillator is used: the phase shifting device being digitally controlled

Family

Application09/652,632Division · filed 31 Aug 2000

Application10/731,779Continuation · filed 9 Dec 2003

Application10/731,779Division · filed 9 Dec 2003

Application11/080,678Continuation · filed 14 Mar 2005

US 2004/0120211 A1Published application

US 6,868,504 B1Related patent

US 6,912,666 B2Related patent

US 7,020,794 B2Related patent

US 2005/0240791 A1This patent

From the US filing history. Foreign family members aren’t listed.

Abstract

Claims47

Dependent claims

(canceled)

A memory device, comprising:

a plurality of memory cells;
and
a plurality of peripheral devices for reading information from said plurality of memory cells, said plurality of peripheral devices comprising a dual locked loop, comprising:
a first locked loop for establishing a phase relationship between an output signal and a reference signal;
a second locked loop responsive to said first locked loop and comprising:
a delay line having a first portion having a plurality of taps for providing a variable amount of load adjustment and a second portion in series with said first portion, said second portion having a plurality of taps for providing a variable amount of drive adjustment;
a control circuit for controlling the amount of load adjustment and drive adjustment such that a tuning range of said delay line is equal to (M/2)(tdl+tdp) where M is the number of taps, tdl is a range of delay provided by said first portion and tdp is a range of delay provided by said second portion;
a phase detector for producing signals for input to said control circuit;
and
a feedback path for connecting an output of said delay line to an input of said first locked loop and to said phase detector, said output signal being available at said output of said delay line.

7 more elements

A system, comprising:

a processor;
a memory device;
and
a bus for interconnecting said processor and said memory device, said memory device comprising a plurality of memory cells and a plurality of peripheral devices for reading information from said plurality of memory cells, said plurality of peripheral devices comprising a dual locked loop, comprising:
a first locked loop for establishing a phase relationship between an output signal and a reference signal;
a second locked loop responsive to said first locked loop and comprising:
a delay line having a first portion having a plurality of taps for providing a variable amount of load adjustment and a second portion in series with said first portion, said second portion having a plurality of taps for providing a variable amount of drive adjustment;
a control circuit for controlling the amount of load adjustment and drive adjustment such that a tuning range of said delay line is equal to (M/2)(tdl+tdp) where M is the number of taps, tdl is a range of delay provided by said first portion and tdp is a range of delay provided by said second portion;
a phase detector for producing signals for input to said control circuit;
and
a feedback path for connecting an output of said delay line to an input of said first locked loop and to said phase detector, said output signal being available at said output of said delay line.

8 more elements

Dependencies are inferred from the claim text.

Interleaved delay line for phase locked and delay locked loops

Life of this patent

Abstract

Claims47

Interleaved delay line for phase locked and delay locked loops

Life of this patent

Abstract

Claims47