Memory system and data channel initialization method for memory system
AssigneeSamsung Electronics Co., Ltd.
InventorsHoe-ju Chung, Jung-bae Lee
Life of this patent
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Abstract
Provided is a memory system and a method that can initialize a data channel at a high speed without the need to increase the number of pins in a semiconductor memory device, and not requiring a circuit to perform an initialization. The memory system includes a memory module equipped with a plurality of semiconductor memory devices; a memory controller controlling the semiconductor memory devices; and a data channel and a command/address channel connected between the plurality of semiconductor memory devices and the memory controller, wherein read latencies and write latencies of the plurality of semiconductor memory devices are controlled by the memory controller.
Claims10
A memory system, comprising:
- a memory module having a plurality of semiconductor memory devices;
- a memory controller controlling the plurality of semiconductor memory devices;
- and
- a data channel and a command/address channel connected between the plurality of semiconductor memory devices and the memory controller,
- wherein read latencies and write latencies for the plurality semiconductor memory devices are controlled by the memory controller.
A data channel initialization method for a memory system, comprising:
- initializing a plurality of semiconductor memory devices;
- applying a write command from a memory controller to the plurality of semiconductor memory devices and writing a data bit pattern from the memory controller to the plurality of semiconductor memory devices;
- applying a read command from the memory controller to the plurality of semiconductor memory devices and reading the written data bit pattern from the plurality of semiconductor memory devices;
- checking delay times as determined by a period defined from a time when the read command is output from the memory controller to a time when first valid data from the data bit patterns read from each of the plurality of semiconductor memory devices arrives at the memory controller;
- and
- determining read latencies for the plurality of semiconductor memory devices according to checked delay times such that a longest delay time becomes identical with other delay times, and providing the read latencies to the plurality of semiconductor memory devices.
Dependencies are inferred from the claim text.