Interrupt control apparatus

An interrupt control apparatus for controlling multiple interrupts, comprising:

• an interrupt information storing unit pre-storing therein, for each of a plurality of interrupt causes, (i) apiece of interrupt processing information for identifying a corresponding interrupt processing program to be executed in response to occurrence of the interrupt cause and (ii) a piece of level information indicating whether an execution level of the corresponding interrupt processing program is a high level or a low level;
• a saving unit operable to save CPU information into both a stack area within a memory indicated by a predetermined register and a protected area that is predetermined within a memory, the CPU information including a content of a processor status word and a content of a program counter within a CPU, and to save a stack pointer which is a content of the predetermined register into the protected area;
• a restoration unit operable to read the saved stack pointer from the protected area, to set the read stack pointer into the predetermined register, and to read the saved CPU information from the protected area and (i) in a case where such part of the CPU information read from the protected area that represents an execution level indicates a low level, to restore, into the CPU, the execution level part and such part of the CPU information saved in the stack area indicated by the predetermined register that represents other than an execution level and (ii) in a case where the execution level part of the CPU information read from the protected area indicates a high level, to restore, into the CPU, the CPU information read from the protected area;
• a protection unit operable to, in a case where an execution level present in the CPU indicates a low level, prevent an instruction for having data written into the protected area from being executed;
• and
• an interrupt control unit operable to, when an interrupt cause has occurred, cause the saving unit to save the CPU information before the interrupt control unit executes the corresponding interrupt processing program, and to cause the restoration unit to restore the CPU information after the execution of the corresponding interrupt processing program is finished.

An interrupt control apparatus for controlling multiple interrupts, comprising:

• an interrupt information storing unit pre-storing therein, for each of a plurality of interrupt causes, (i) a piece of interrupt processing information for identifying a corresponding interrupt processing program to be executed in response to occurrence of the interrupt cause and (ii) a piece of level information indicating whether an execution level of the corresponding interrupt processing program is a high level or a low level;
• a saving unit operable to save CPU information into a stack area within a memory indicated by a predetermined register, the CPU information including a content of a processor status word and a content of a program counter within a CPU, and to save a stack pointer which is a content of the predetermined register into a protected area within a memory;
• a restoration unit operable to read the saved stack pointer from the protected area, to set the read stack pointer into the predetermined register, and to read the CPU information from the stack area indicated by the predetermined register, and to restore the read CPU information into the CPU;
• a first protection unit operable to, in a case where an execution level present in the CPU indicates a low level, prevent an instruction for having data written into the protected area from being executed;
• a second protection unit operable to, in the case where the execution level present in the CPU indicates a low level, prevent an instruction from being executed, the instruction being for having data written into one of stack areas indicated by stack pointers that are saved in the protected area and not yet read out;
• and
• an interrupt control unit operable to, when an interrupt cause has occurred, cause the saving unit to save the CPU information before the interrupt control unit executes the corresponding interrupt processing program, and to cause the restoration unit to restore the CPU information after the execution of the corresponding interrupt processing program is finished.