DCT processor used for implementing discrete cosine transform (DCT)

A DCT processor used for implementing discrete cosine transform comprising:

• the storage processor having a plurality of input units and a plurality of the output units, the storage processor for permutating a plurality of items of data inputted through the plurality of the input units and then outputting the data from the plurality of the output units;
• a computing device having a plurality of input units connected to the output units of the storage processor and a plurality of output units, the computing device for computing data inputted from the plurality of the input units in accordance with a given DCT algorithm and outputting the data from the plurality of the output units;
• a storage device having a plurality of input units connected to the output units of the computing device and a plurality of output units connected to the input units of the storage processor, the storage device for storing a plurality of items of data outputted from the output units of the computing device and outputting the data from the plurality of the output units;
• and
• a sorting module disposed between the storage device and the storage processor, the sorting module for sorting data from the storage device in a given order,
• wherein the plurality of items of data outputted from the output units of the storage device is looped at a given number of times by the storage processor, the computing device, the storage device, and the sorting module in this order, and
• a result of discrete cosine transform is determined based on the data read out of the output unit of the storage device.

A 32-point DCT processor for performing discrete cosine transform with respect to 32 items of data obtained by being sampled at 32 sampling points comprising:

• a storage processor having eight input units and eight output units, the storage processor for allowing eight items of data to be inputted and outputted each at one time, at four times in total, thus a total of 32 items of data, and the storage processor for outputting a total of 32 items of data that has been sequentially written at given storage locations eight items each at one time, at four times in total, to the eight output units in a given order through the eight input units;
• two computing devices, each having four input units connected to four output units among the eight output units of the storage processor and four output units, the computing devices for computing data inputted from the eight input units by four items of data each at one time in accordance with a CGA-DCT algorithm and outputting the data from the four output units;
• a storage device having eight input units connected to the eight output units in total of the two computing devices and eight output units connected to the eight input units in total of the storage processor, the storage device allowing eight items of data to be written in and read out each at one time, at four times in total, thus a total of 32 items of data by first-in, first-out, and the storage device for storing eight items of data in total outputted from the individual output units of the computing device at four times in total, thus a total of 32 items of data;
• and
• a sorting module disposed between the storage device and the storage processor, the sorting module for sorting data from the storage device in a given order.

A storage processor used for a DCT processor used for implementing discrete cosine transform, the storage processor comprising:

• a plurality of input units;
• and
• a plurality of output units,
• wherein a plurality of items of data inputted through the plurality of the input units is permutated and is outputted from the plurality of the output units,
• wherein the DCT processor further comprises:
• a computing device having a plurality of input units connected to the output units of the storage processor and a plurality of the output units, the computing device for computing data inputted from the plurality of the input units in accordance with a given DCT algorithm and outputting the data from the plurality of the output units;
• a storage device having a plurality of input units connected to the output units of the computing device and a plurality of output units connected to the input units of the storage processor, the storage device for storing a plurality of items of data outputted from the output units of the computing device and outputting the data from the plurality of the output units;
• and
• a sorting module disposed between the storage device and the storage processor, the sorting module for sorting data from the storage device in a given order,
• wherein a plurality of items of data outputted from the storage device is looped at a given number of times by the storage processor, the computing device, the storage device, and the sorting module in this order, and
• a result of discrete cosine transform is determined based on data read out of the output units of the storage device.

A storage processor used for a 32-point DCT processor for performing discrete cosine transform with respect to 32 items of data obtained by being sampled at 32 sampling points, the storage processor comprising:

• eight input units;
• and
• eight output units,
• wherein the storage processor allows eight items of data to be inputted and outputted each at one time at four times in total, thus a total of 32 items of data, and sequentially outputs a total of 32 items of data that has been sequentially written at given storage locations eight items each at one time, at four times in total, to the eight output units in a given order through the eight input units,
• wherein the DCT processor further comprises:
• two computing devices, each having four input units connected to four output units among the eight output units of the storage processor and four output units, the computing devices for computing data inputted from the eight input units by four items of data each at one time in accordance with a CGA-DCT algorithm and outputting the data from the four output units;
• a storage device having eight input units connected to the eight output units in total of the two computing devices and eight output units connected to the eight input units in total of the storage processor, the storage device allowing eight items of data to be written in and read out each at one time, at four times in total, thus a total of 32 items of data by first-in, first-out, and the storage device for storing eight items of data in total outputted from the individual output units of the computing device at four times in total, thus a total of 32 items of data;
• and
• a sorting module disposed between the storage device and the storage processor, the sorting module for sorting data from the storage device in a given order.