# US 2005/0239255 A1 · Formation of lattice-tuning semiconductor substrates

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- Number: US 2005/0239255 A1
- Document ID: US20050239255A1
- Status: Published application
- Kind: A1
- Application number: 10/514,941
- Filed: 2003-05-30
- Published: 2005-10-27
- Earliest claimed: 2002-05-31
- Assignees: University of Warwick
- Inventors: Adam Capewell; Timothy Grasby; Evan Hubert Parker; Terence Whall
- Web page: https://patentgrep.com/patent/US20050239255A1

## CPC

- C30B 23/02: Epitaxial-layer growth
- C30B 25/02: Epitaxial-layer growth
- C30B 29/52: Alloys
- H10P 14/20: of semiconductor materials
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3251: {consisting of three or more layers}
- H10P 14/3254: {Graded layers}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- C30B: SINGLE-CRYSTAL GROWTH (by using ultra-high pressure, e.g. for the formation of diamonds, B01J3/06); UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL (zone-refining of metals or alloys C22B); PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (casting of metals, casting of other substances by the same processes or devices B22D; working of plastics B29; modifying the physical structure of metals or alloys C21D, C22F); SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (for producing semiconductor devices or parts thereof H10); APPARATUS THEREFOR
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In order to reduce dislocation pile-ups in a virtual substrate, a buffer layer 32 is provided, between an underlying Si substrate 34 and an uppermost constant composition SiGe layer 36, which comprises alternating graded SiGe layers 38 and uniform SiGe layers 40. During the deposition of each of the graded SiGe layers 38 the Ge fraction x is linearly increased from a value corresponding to the Ge composition ratio of the preceding layer to a value corresponding to the Ge composition ratio of the following layer. Furthermore the Ge fraction x is maintained constant during deposition of each uniform SiGe layer 40, so that the Ge fraction x varies in step-wise fashion through the depth of the buffer layer. After the deposition of each pair of graded and uniform SiGe layers 38 and 40, the wafer is annealed at an elevated temperature greater than the temperature at which the layers have been deposited. Each graded SiGe layer is permitted to relax by pile-ups of dislocations, but the uniform SiGe layers 40 prevent the pile-ups of dislocations from extending out of the graded SiGe layers 38. Furthermore each of the subsequent annealing steps ensures that the previously applied graded and uniform SiGe layers 38 and 40 are fully relaxed in spite of the relative thinness of these layers. As a result the dislocations are produced substantially independently within surcessive pairs of layers 38 and 40, and are relatively evenly distributed with only small surface undulations 40 being produced. Furthermore the density of threading dislocations is greatly reduced, thus enhancing the performance of the virtual substrate by decreasing the disruption of the atomic lattice which can lead to scattering of electrons in the active devices and degradation of the speed of movement of the electrons.

## Claims

### Claim 1

A method of forming a lattice-tuning semiconductor substrate, comprising:
(a) epitaxially growing on a Si surface a first graded SiGe layer having a Ge composition ratio which increases across the layer from a minimum value to a first level;
(b) epitaxially growing on top of the first graded SiGe layer a first uniform SiGe layer having a Ge composition ratio at said first level which is substantially constant across the layer;
(c) annealing at least the first graded SiGe layer at an elevated temperature in order to substantially fully relieve the strain in the SiGe layers; and
(d) epitaxially growing on top of the first uniform SiGe layer a second graded SiGe layer having a Ge composition ratio which increases across the layer from said first level to a second level greater than said first level.

### Claim 2 (depends on 1)

A method according to claim 1, wherein the annealing step (c) occurs after the growth of the first uniform SiGe layer and before the growth of the second graded SiGe layer.

### Claim 3 (depends on 1)

A method according to claim 1, further comprising epitaxially growing on top of the second graded SiGe layer a second uniform SiGe layer having a Ge composition ratio at said second level which is substantially constant across the layer.

### Claim 4 (depends on 3)

A method according to claim 3, wherein further graded and uniform SiGe layers are epitaxially grown on top of the first and second SiGe layers with the SiGe composition ratio increasing across the or each graded SiGe layer from the level of the preceding uniform SiGe layer to an increased level.

### Claim 5 (depends on 3)

A method according to claim 3, wherein the epitaxial growth of at least one of the second and further uniform SiGe layers is followed by a further annealing step at an elevated temperature similar to the annealing step (c).

### Claim 6 (depends on 4)

A method according to claim 4, wherein each epitaxial growth step is carried out at a temperature in the range of 350 to 1000° C.

### Claim 7 (depends on 1)

A method according to claim 1, wherein the or each annealing step is carried out at an elevated temperature in the range of 500 to 1200° C.

### Claim 8 (depends on 1)

A method according to claim 1, wherein the epitaxial growth steps are effected by molecular beam epitaxy (MBE).

### Claim 9 (depends on 1)

A method according to claim 1, wherein the epitaxial growth steps are effected by chemical vapour deposition (CVD).

### Claim 10 (depends on 1)

A method according to claim 1, wherein the surface roughness of at least some of the graded and uniform SiGe layers is lowered by the addition of one or more surfactants.

### Claim 11 (depends on 1)

A method according to claim 1, wherein a thin layer containing a high density of point defects is grown immediately prior to the growth of at least one of the graded SiGe layers.

### Claim 12 (depends on 1)

A method according claim 1, further comprising the step of growing on top of the graded and uniform SiGe layers a strained Si layer within which one or more semiconductor devices are formed.

### Claim 13 (depends on 1)

A lattice-tuning semiconductor substrate formed by a method according claim 1.

### Claim 14 (depends on 13)

A lattice-tuning semiconductor substrate according to claim 13, incorporating a strained Si layer within which one or more semiconductor devices are formed.