Vertical floating gate transistor
AssigneeMicron Technology, Inc.
InventorPaul Rudeck
Life of this patent
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Abstract
A floating gate transistor has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a control gate are fabricated vertically to control current conducted through the transistor. The control gate is coupled to a word line that is formed with the control gates and extends in a common horizontal direction.
Claims20
A method for fabricating a pair of non-volatile memory cells, the method comprising:
- forming a trench in a substrate;
- implanting a drain region in the substrate substantially adjacent to and on each side of the top of the trench;
- implanting a source region in the substrate under the trench;
- forming first and second floating gates adjacent to and on opposite sides of the trench;
- forming first and second control gates as a single unit in the trench;
- and
- forming a wordline in each trench such that the wordline is structurally separate from but connected to the first and second control gates, the wordline parallel to and between the first and second control gates.
A method for fabricating a memory array, the method comprising:
- creating a first plurality of parallel trenches in a substrate;
- forming an oxide in the first plurality of parallel trenches;
- creating a second plurality of parallel trenches in the substrate, wherein the second plurality of parallel trenches is substantially perpendicular to the first plurality of parallel trenches to form a plurality of substrate material pillars that are separated in a first direction by the oxide and a second direction by the second plurality of trenches;
- implanting a source region at a bottom of each of the second plurality of trenches and a drain region at the top of each of the plurality of pillars;
- fabricating a pair of floating gates in each of the second series of parallel trenches;
- fabricating a pair of control gates in each of the second series of parallel trenches, the pair of control gates formed as a single unit between the pair of floating gates;
- and
- fabricating a wordline substantially parallel to and between each pair of control gates, the wordline being structurally separate from but connected to each pair of control gates.
A method for fabricating a flash memory device comprising an array of flash memory cells, the method comprising:
- forming a layer of nitride on a substrate;
- etching a first plurality of substantially parallel trenches in the layer of nitride;
- depositing a layer of thin oxide in the first series of substantially parallel trenches;
- planarizing the layer of thin oxide to leave the first plurality of trenches filled with oxide;
- forming a second plurality of substantially parallel trenches in the substrate, wherein the second plurality of trenches is substantially perpendicular to the first plurality of trenches such that a plurality of substrate material pillars are formed and separated in a first direction by the oxide and a second direction by the second plurality of trenches;
- implanting source regions at the bottom of each of the second plurality of trenches and drain regions at the top of each pillar;
- fabricating a pair of floating gates in each of the second plurality of trenches;
- fabricating a pair of control gates in each of the second plurality of trenches;
- and
- fabricating a wordline substantially parallel to and between each pair of control gates, the wordline being structurally separate from but connected to each pair of control gates.
Dependencies are inferred from the claim text.