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US 2005/0239246 A1Published application
Method and apparatus for fabricating a memory device with a dielectric etch stop layer
AssigneeMicron Technology, Inc.
InventorH. Manning
Life of this patent
Estimating the term…
Abstract
The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS gates, NMOS gates, memory cells, P+ active areas, and N+ active areas. These structures are fabricated through the use of multiple masking processes, which may cause shorts when a buried digit layer is deposited if the masking processes are misaligned. Accordingly, a dielectric etch stop layer, such as aluminum oxide Al2O3 or silicon carbide SiC, may be utilized in the array to prevent shorts between the wordlines, active areas, and the buried digit layer when the contacts are misaligned.
Claims43
A method for fabricating a device, the method comprising:
- depositing a dielectric etch stop layer over an array portion of a substrate and a peripheral portion of the substrate;
- removing the dielectric etch stop layer from the peripheral portion of the substrate;
- and
- removing only a portion of the dielectric etch stop layer from the array portion of the substrate.
1 more element
A method for fabricating a device with a dielectric etch stop layer, the method comprising:
- forming a first plurality of structures in an array portion of a substrate and a second plurality of structures in the peripheral portion of the substrate;
- depositing a dielectric etch stop layer over the first plurality of structures and the second plurality of structures;
- removing the dielectric etch stop layer from the second plurality of structures;
- etching a pattern into the dielectric etch stop layer to expose at least one of the first plurality of structures;
- depositing a dielectric layer over the first plurality of structures in the array portion of the substrate and the second plurality of structures in the peripheral portion of the substrate;
- and
- removing a portion of the dielectric layer with an etchant to expose at least one of the first plurality of structures and at least one of the second plurality of structures, wherein the etchant is more selective to the dielectric layer than the dielectric etch stop layer.
4 more elements
A method for fabricating a device comprising:
- forming a plurality of wordlines over an array portion and a peripheral portion of a substrate;
- forming a plurality of spacers, each of the plurality of spacers being adjacent to one of the plurality of wordlines;
- depositing a dielectric etch stop layer over each of the plurality of spacers, the plurality of wordlines, the array portion and the peripheral portion of the substrate;
- depositing a photoresist layer over the dielectric etch stop layer;
- etching the photoresist layer and the dielectric etch stop layer to expose the substrate in the peripheral portion adjacent to at least one of the plurality of wordlines in the peripheral portion;
- doping a plurality of active areas in the peripheral portion adjacent to the at least one of the plurality of wordlines;
- depositing a plurality of conductive plugs between at least a portion of the plurality of spacers in the array portion;
- depositing a dielectric layer over at least a portion of the dielectric etch stop layer and the peripheral portion;
- etching into the dielectric layer with an etchant to expose at least one of at least one of the plurality of active areas in the peripheral portion and at least one of the plurality of wordlines in the peripheral portion and at least one of the plurality of conductive plugs in the array portion, wherein the etchant is more selective to the dielectric layer than the dielectric etch stop layer;
- and
- depositing a buried digit layer over each of the dielectric etch stop layer, the dielectric layer, the at least one of the at least one of the plurality of active areas in the peripheral portion and the at least one of the plurality of wordlines in the peripheral portion and the at least one of the plurality of conductive plugs in the array portion to form a local interconnect between the array portion and the peripheral portion.
8 more elements
A device comprising:
- an array portion of a substrate comprising a first plurality of spacers, a first plurality of wordlines associated with at least one of the first plurality of spacers, and a first plurality of active areas adjacent to at least one of the first plurality of wordlines, wherein a dielectric etch stop layer is deposited over each of a portion of the first plurality of spacers, a portion of the first plurality of wordlines, and a portion of the first plurality of active areas;
- a peripheral portion of the substrate comprising a second plurality of spacers, a second plurality of wordlines associated with at least one of the second plurality of spacers, and a second plurality of active areas adjacent to at least one of the second plurality of wordlines;
- and
- a conductive layer electrically coupled to at least one of the first plurality of active areas and one of at least one of the second plurality of active areas and at least one of the second plurality of wordlines, wherein the conductive layer forms an interconnect between the array portion and the peripheral portion.
1 more element
A system comprising:
- a processor;
- and
- a memory device coupled to the processor comprising:
- an array portion of a substrate comprising a first plurality of wordlines, a first plurality of active areas adjacent to at least one of the first plurality of wordlines, and a first plurality of conductive plugs associated with the first plurality of active areas, wherein a dielectric etch stop layer is deposited over each of a portion of the first plurality of wordlines, a portion of the first plurality of active areas, and a portion of the first plurality of conductive plugs;
- a peripheral portion of the substrate comprising a second plurality of wordlines and a second plurality of active areas adjacent to at least one of the second plurality of wordlines;
- and
- a conductive layer electrically coupled to one of at least one of the first plurality of conductive plugs and at least one of the first plurality of active areas and at least one of the second plurality of active areas, wherein the conductive layer forms an interconnect between the array portion and the peripheral portion.
4 more elements
A device comprising:
- an array portion comprising a first plurality of structures;
- a peripheral portion comprising a second plurality of structures;
- and
- a dielectric etch stop layer disposed over the array portion and the peripheral portion, wherein the dielectric etch stop layer is subsequently removed from the peripheral portion and only partially removed from the array portion.
1 more element
Dependencies are inferred from the claim text.