High speed lateral heterojunction MISFETS realized by 2-dimensional bandgap engineering and methods thereof

A method of preparing an inverter made of lateral channel field effect transistors comprising the steps of (FIG. 6):

• forming a first transistor comprising the steps of:
• forming a silicon layer 31 on a first single crystalline substrate 30, doping said silicon layer 31 p-type,
• forming a strained Si1-yCy epitaxial region 32 and 33 over said p-type silicon layer 31, doping the above strained Si1-yCy layer 32, 33 n-type to a concentration level greater than 1E19 cm−3,
• forming a thin silicon layer 34 over the above n-type strained Si1-yCy epitaxial layer 32, 33, and p-type silicon 31,
• forming a dielectric layer 50 serving as device isolation,
• forming a thin dielectric layer 35 over the above silicon layer 34,
• forming a conducting layer 36 over the above dielectric layer 35,
• forming a gate stack 888 comprising both the above dielectric layer 35 and the conducting layer 36, which overlaps the silicon 31 and the part of the strained Si1-yCy 32, 33,
• forming a blanket dielectric layer 37 over and above the gate stack 888,
• forming a dielectric layer 38 on the sidewall of the gate stack 888,13
• forming a second transistor comprising the steps of:
• forming a silicon layer 131 on a first single crystalline substrate 30, doping said silicon layer 131 n-type,
• forming a compressively strained Si1-xGex epitaxial region 132 and 133 in said p-type silicon layer 31, doping the above strained Si1-xGex layer 132 and 133 p-type to a concentration level greater than 1E19 cm−3,
• forming a thin silicon or a compressively strained Si1-wGew layer 134 over the above p-type strained Si1-xGex epitaxial layer 132, 133 and n-type silicon 131,
• forming a thin dielectric layer 135 over the above layer 134, and
• forming a conducting layer 136 over the above dielectric layer 135,
• forming a gate stack comprising both the above dielectric layer 135 and the conducting layer 136, which overlaps the silicon 131 and part of region 132, 133.

The method according to claim 29 further comprising the steps of:

• forming a blanket dielectric layer 137 over and above the gate stack 666,
• forming a dielectric layer 138 on the sidewall of the gate stack 666′,
• forming a blanket dielectric layer 39 over the entire structure,
• forming a conducting layer 40 through the above blanket dielectric layer 39 in contact to the silicon layer 34 in the region on top of the n-type 33,
• forming a conducting layer 42 through the above blanket dielectric layer 39 in contact to the silicon layer 34 in the region on top of the n-type 32,
• forming a conducting layer 41 through the above blanket dielectric layer 39 and 37 in contact to the conducting layer 36 at the top of the gate stack 888,
• forming a conducting layer 142 through the above blanket dielectric layer 39 in contact to layer 134 in the region on top of the n-type layer 133,
• forming a conducting layer 140 through the above blanket dielectric layer 39 in contact to layer 134 in the region on top of the n-type layer 132,
• forming a conducting layer 141 through the above blanket dielectric layer 39 and 137 in contact to the conducting layer 136 at the top of the gate stack 666, and
• forming dielectric region 50 on layer 30 or 30′ in between region 31 and 131 to serve as device isolation.

A method of preparing an inverter made of lateral channel field effect transistors comprising the steps of (FIG. 7):

• forming a first transistor comprising the steps of:
• forming a relaxed SiGe layer 531 on a first single crystalline substrate 30, doping said SiGe layer 531 p-type,
• forming a strained silicon epitaxial region 532 and 533 over said p-type SiGe layer 531, doping the above strained silicon layer 532, 533 n-type to a concentration level greater than 1E19 cm−3,
• forming a thin strained silicon layer 534 over the above n-type strained silicon epitaxial layer 532, 533, and p-type SiGe 531,
• forming a dielectric layer 50 served as device isolation,
• forming a thin dielectric layer 35 over the above silicon layer 534,
• forming a conducting layer 36 over the above dielectric layer 35,
• forming a gate stack 888 comprising both the above dielectric layer 35 and the conducting layer 36, which overlaps SiGe 531 and the part of the strained silicon region 532, 533,
• forming a blanket dielectric layer 37 over and above the gate stack 888,13
• forming a dielectric layer 38 on the sidewall of the gate stack 888′_,
• forming a second transistor comprising the steps of:
• forming a silicon layer 131 on a first single crystalline substrate 30, doping said silicon layer 131 n-type,
• forming a compressively strained Si1-xGex epitaxial region 132 and 133 over said p-type silicon layer 131, doping the above strained Si1-xGex layer 132 and 133 p-type to a concentration level greater than 1E19 cm−3,
• forming a thin silicon or a compressively strained Si1-wGew layer 134 over the above p-type strained Si1-xGex epitaxial layer 132, 133 and n-type silicon 131,
• forming a thin dielectric layer 135 over the above layer 134, and
• forming a conducting layer 136 over the above dielectric layer 135,
• forming a gate stack comprising both the above dielectric layer 135 and the conducting layer 136, which overlaps the silicon 131 and part of region 132, 133.