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US 2005/0237828 A1Published application
Distributed loop components
AssigneeIntel Corporation
InventorsJoseph Kennedy, Stephen Mooney
Life of this patent
Estimating the term…
Abstract
In some embodiments, a chip includes a chip interface to accept a delay control signal from outside the chip. The chip also includes a controllable delay line to delay an input signal responsive to the delay control signal to provide an output signal with a particular phase relationship to the input signal. Other embodiments are described and claimed.
Claims39
A chip comprising:
- a chip interface to accept a delay control signal from outside the chip;
- and
- a controllable delay line to delay an input signal responsive to the delay control signal to provide an output signal with a particular phase relationship to the input signal.
A chip comprising:
- a chip interface to accept a signal from outside the chip;
- a state machine to provide a delay control signal responsive to the signal from outside the chip;
- and
- a controllable delay line to delay an input signal responsive to the delay control signal to provide an output signal with a particular phase relationship to the input signal.
1 more element
A system comprising:
- a first chip including:
- a chip interface to accept a delay control signal from outside the chip;
- and
- a controllable delay line to delay an input signal responsive to the delay control signal to provide an output signal with a particular phase relationship to the input signal;
- and
- a second chip including:
- at least a portion of a delay controller to receive a signal indicative of a phase difference between the input and output signals and in response thereto to provide the delay control signal.
4 more elements
A system comprising:
- a first chip including:
- a chip interface to receive a signal from outside the chip;
- a state machine to provide a delay control signal responsive to the signal from outside the chip;
- and
- a controllable delay line to delay an input signal responsive to the delay control signal to provide an output signal with a particular phase relationship to the input signal;
- and
- a second chip including:
- a portion of a delay controller to receive a signal indicative of a difference between the input and output signals and in response thereto to provide an initial delay control signal;
- and
- wherein the delay control signal is provided from the second chip to the chip interface of the first chip.
7 more elements
A system comprising:
- a first chip including:
- a chip interface to receive a signal from outside the chip;
- a state machine to provide a delay control signal responsive to the signal from outside the chip;
- and
- a controllable delay line to delay an input signal responsive to the delay control signal to provide an output signal with a particular phase relationship to the input signal;
- and
- a second chip including:
- signal providing circuitry to provide a scan input signal to the chip interface of the first chip;
- and
- signal evaluation circuitry to receive a scan output signal from the first chip and to evaluate the controllable delay line there from.
7 more elements
A system comprising:
- a first chip including:
- a chip interface to receive a delay control signal from outside the chip;
- a controllable delay line to delay an input signal responsive to the delay control signal to provide an output signal with a particular phase relationship to the input signal;
- and
- a second chip including:
- signal providing circuitry to provide a scan input signal to the chip interface of the first chip;
- and
- signal evaluation circuitry to receive a scan output signal from the first chip and to evaluate the controllable delay line there from.
5 more elements
Dependencies are inferred from the claim text.