Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memory
AssigneeMacronix International Co., Ltd.
InventorsYen-Hao Shih, Hang-Ting Lue
Life of this patent
Estimating the term…
Abstract
A memory cell with a charge trapping structure has multiple bias arrangements. Multiple cycles of applying the bias arrangements lowering and raising a threshold voltage of the memory cell leave a distribution of charge in the charge trapping layer. The charge interferes with the threshold voltage achievable in the memory cell. This distribution of charge is balanced by applying a charge balancing bias arrangement. The memory cell has a high work function gate, which causes the equilibrium state of the charge balancing bias arrangement to result in a lower threshold voltage.
Claims16
An integrated circuit device comprising:
- a substrate;
- a plurality of memory cells on the substrate, each memory cell of the plurality of memory cells having a threshold voltage and comprising a charge trapping structure, a gate, and source and drain regions in the substrate, and including a top dielectric, a charge trapping structure, and a bottom dielectric between the gate and the channel, wherein the gate comprises a material having a work function higher than n-type polysilicon;
- and
- controller circuitry coupled to the plurality of memory cells, including logic to apply a charge balancing bias arrangement, and wherein the top dielectric, the charge trapping structure, and the bottom dielectric have a combined effective oxide thickness, and the bottom dielectric has an effective oxide thickness greater than 3 nanometers, and the charge balancing bias arrangement includes a negative voltage from the gate of the memory cell to the substrate in the region of the channel having a magnitude of about 0.7 or higher volts per nanometer of the combined effective oxide thickness.
An integrated circuit device comprising:
- a substrate;
- a plurality of memory cells on the substrate, each memory cell of the plurality of memory cells having a threshold voltage and comprising a charge trapping structure, a gate, and source and drain regions in the substrate, and including a top dielectric, a charge trapping structure, and a bottom dielectric between the gate and the channel, wherein the gate comprises a material having a work function higher than n-type polysilicon;
- and
- controller circuitry coupled to the plurality of memory cells, including logic to apply a charge balancing bias arrangement, and wherein the top dielectric, the charge trapping structure, and the bottom dielectric have a combined effective oxide thickness, and the bottom dielectric has an effective oxide thickness about 3 nanometers or less, and the charge balancing bias arrangement includes a negative voltage from the gate of the memory cell to the substrate in the region of the channel having a magnitude of about 0.3 or higher volts per nanometer of the combined effective oxide thickness.
Dependencies are inferred from the claim text.