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US 2005/0232020 A1Published application
Memory system including a circuit to convert between parallel and serial bits
AssigneeRambus Inc.
InventorsRichard Perego, Fredrick Ware
Life of this patent
Estimating the term…
Abstract
A memory controller comprises a circuit to convert a set of parallel constituent bits to a serial stream of constituent bits. A first output driver receives at least four bits of the serial stream of constituent bits in succession from the circuit. The first output driver outputs the at least four bits of the serial stream of constituent bits onto a first external signal line.
Claims24
1-22. (canceled)
A memory controller comprising:
- a circuit to convert a set of parallel constituent bits to a serial stream of constituent bits;
- and
- a first output driver to receive at least four bits of the serial stream of constituent bits in succession from the circuit, the first output driver to output the at least four bits of the serial stream of constituent bits onto a first external signal line.
A integrated circuit device comprising:
- a first receiver to receive a first serial stream of at least four bits from a first external signal line;
- a second receiver to receive a second serial stream of at least four bits from a second external signal line;
- and
- a deserializing circuit coupled to the receiver, the deserializing circuit to receive the first serial stream and the second serial stream, the deserializing circuit to convert the first serial stream of the at least four bits into a first set of at least four parallel bits for storage in a row of storage cells, and the deserializing circuit to convert the second serial stream of the at least four bits into a second set of at least four parallel bits for storage in the row of storage cells.
1 more element
A memory system comprising:
- a memory controller to output data values as a respective plurality of serial streams of bits;
- a plurality of signal lines coupled to the memory controller, each signal line of the plurality of signal lines to carry a respective serial stream of bits of the plurality of serial streams of bits;
- and
- at least one integrated circuit device coupled to the plurality of signal lines, the at least one integrated circuit device coupled to receive the plurality of serial streams of bits from the memory controller over the plurality of signal lines, the at least one integrated circuit device to convert a serial stream of bits in the respective plurality of serial streams of bits to a set of parallel bits for storage in a row of storage cells.
1 more element
A memory controller comprising:
- a shift register to receive a set of bits in parallel from a plurality of signal lines, wherein the set of bits is a data value that has an associated mask value;
- and
- an output driver to receive the set of bits from the shift register, the output driver to output the set of bits as a serial stream onto an external signal line.
A memory controller comprising:
- a circuit to receive concurrently a plurality of input signals at a plurality of respective inputs, the plurality of input signals correspond to a plurality of bit values that has an associated mask value, the circuit to output a plurality of signals in succession corresponding to the plurality of bit values, each signal in the plurality of signals is output in response to an edge of a clock signal;
- and
- a first output driver to receive at least four signals of the plurality of signals from the circuit, the first output driver to provide at least four output signals in succession onto an external signal line, the at least four output signals corresponding to at least four bit values in the plurality of bit values.
Dependencies are inferred from the claim text.