Non-volatile semiconductor memory and manufacturing method thereof

A method of manufacturing a non-volatile semiconductor memory, comprising:

• a step of providing a control gate trough through an electric charge accumulating portion on a semiconductor substrate;
• a step of providing a drain region by introducing an impurity outwardly of one edge of said control gate on said semiconductor substrate in self-alignment with the edge thereof;
• a step of providing a side wall insulating layer on a side surface of said control gate;
• and
• a step of providing a source region by introducing the impurity outwardly of said side wall insulating layer on said semiconductor substrate in self-alignment with said side wall insulating layer.

A method of manufacturing a non-volatile semiconductor memory, comprising:

• a step of providing a floating gate material layer through a channel insulating layer on a semiconductor substrate;
• a step of providing a control gate material layer through an inter-layer insulating layer on said floating gate material layer;
• a step of providing a control gate and a floating gate by sequentially patterning said control gate material layer and said floating gate material layer;
• a step of providing a drain region by introducing an impurity outwardly of one edge of said control gate on said semiconductor substrate in self-alignment with the edge thereof;
• a step of providing a side wall insulating layer on side surfaces of said control gate and of said floating gate;
• and
• a step of providing a source region by introducing the impurity outwardly of said side wall insulating layer on said semiconductor substrate in self-alignment with said side wall insulating layer.

A method of manufacturing a non-volatile semiconductor memory, comprising:

• a step of providing a control gate trough an electric charge, accumulating portion on a semiconductor substrate;
• a step of providing a first side wall insulating layer on a side surface of said control gate;
• a step of providing a drain region by introducing an impurity outwardly of said first side wall insulating layer on said semiconductor substrate in self-alignment with said first side wall insulating layer;
• a step of providing a second side wall insulating layer on a side surface of said first side wall insulating layer;
• and
• a step of providing a source region by introducing the impurity outwardly of said second side wall insulating layer on said semiconductor substrate in self-alignment with said second side wall insulating layer.

A method of manufacturing a non-volatile semiconductor memory, comprising:

• a step of providing a floating gate material layer through a channel insulating layer on a semiconductor substrate;
• a step of providing a control gate material layer through an inter-layer insulating layer on said floating gate material layer;
• a step of providing a control gate and a floating gate by sequentially patterning said control gate material layer and said floating gate material layer;
• a step of providing a first side wall insulating layer on side surfaces of said control gate and of said floating gate;
• a step of providing a drain region by introducing an impurity outwardly of said first side wall insulating layer on said semiconductor substrate in self-alignment with said first side wall insulating layer;
• a step of providing a second side wall insulating layer on a side surface of said first side wall insulating layer;
• and
• a step of providing a source region by introducing the impurity outwardly of said second side wall insulating layer on said semiconductor substrate in self-alignment with said second side wall insulating layer.