Memory devices with page buffer having dual registers and metod of using the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJune Lee, Oh-Suk Kwon, Heung-Soo Im
Life of this patent
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Abstract
A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.
Claims23
A nonvolatile memory device comprising:
- an array of memory cells to store data;
- a Y-gating circuit to gate data stored in a group of the memory cells;
- and
- a page buffer circuit coupled between the memory cell array and the Y-gating circuit,
- wherein the page buffer circuit comprises
- a first latch having a first latch node and a second latch node;
- a first switch configured to connect the first latch node to a sense line;
- a second switch configured to connect the first latch node to a data line via the Y-gating circuit;
- a reset part configured to reset the first latch;
- a third switch connected to the sense line and the second latch node and configured to discharge the second latch node;
- a current source configured to supply a current to the sense line;
- a second latch having a third latch node and fourth latch node;
- a set part configured to set the second latch;
- a fourth switch connected to the sense line and the third latch node and configured to discharge the third latch node;
- a fifth switch configured to isolate the third latch node from the sense line;
- a sixth switch configured to connect either one of the third and fourth latch notes to the data line via the column gate circuit;
- and
- a seventh switch connected to the first latch node and configured to output program pass/fail information.
The nonvolatile memory device comprising:
- an array of memory cells to store data;
- a Y-gating circuit to gate data stored in a group of the memory cells;
- and
- a page buffer circuit coupled between the memory cell array and the Y-gating circuit,
- wherein the page buffer circuit comprises
- a first latch having a first latch node and a second latch node;
- a first switch connected to the first latch node, a sense line, and the Y-gating circuit;
- a reset part configured to reset the first latch;
- a second switch connected to the sense line and the second latch node and confirgured to discharge the second latch node;
- a current source configured to supply a current to the sense line;
- a second latch having a third latch node and a fourth latch node;
- a set part configured to set the second latch;
- a third switch connected to the sense line and the third latch node and configured to discharge the third latch node;
- a fourth switch configured to isolate the third latch node from the sense line;
- a fifth switch configured to connect either one of the third and fourth latch nodes to the data line via the column gate circuit;
- and
- a sixth switch connected to the first latch node and configured to output program pass/fail information.
A program method for a memory system comprising:
- providing a first data to be programmed to a nonvolatile memory device;
- then storing the first data at a first register of a page buffer in the nonvolatile memory device through a Y-gating circuit;
- then storing the first data at a second register of the page buffer in the nonvolatile memory device through a sense node;
- and then storing the first data at a first cell of a memory cell array in the nonvolatile memory device through the sense node.
Dependencies are inferred from the claim text.