Semiconductor integrated circuit device and magnetic memory device capable of maintaining data integrity

A magnetic memory device comprising:

• at least one memory cell array having a plurality of magnetic memory cells arranged in rows and columns, each magnetic memory cell including a magneto-resistance element having a fixed layer and a free layer each having a magnetization-easy axis and a magnetization-hard axis, said free layer having a magnetization direction set according to storage data, and said fixed layer having a magnetization direction fixedly set independently of the storage data;
• an inverting data holding circuit arranged commonly to the memory cells of said at least one memory cell array, for fixedly storing inversion control data inverting a logical level of at least one of write data and read data of said at least one memory cell array;
• and
• a data polarity inverting circuit for inverting the logical level of one of the write data and the read data of said at least one memory cell array according to the inversion control data received from said inverting data holding circuit.

A magnetic memory device comprising:

• a plurality of magnetic memory cells arranged in rows and columns;
• a plurality of bit lines arranged corresponding to the memory cell columns;
• a plurality of bit line drivers arranged on opposite sides of the respective bit lines, and supplying currents to corresponding bit lines when being active, each bit line driver including a charging transistor coupled to a power supply node and a discharging driver coupled to a ground node;
• and
• a plurality of bit line drive control circuits arranged corresponding to the respective bit line drivers, and activating corresponding bit line drivers according to a column select signal and write data, the bit line drive control circuits arranged corresponding to a common bit line driving the charging transistor of one of the bit line drivers on opposite sides of the common bit line and the discharging transistor of the other bit line driver for the common bit line into a conductive state at different timings when being selected.

A magnetic memory device comprising:

• a plurality of magnetic memory cells arranged in rows and columns;
• a plurality of bit lines arranged corresponding to the memory cell columns;
• a plurality of digit lines arranged corresponding to the memory cell rows;
• a plurality of column select signal lines, arranged in parallel to the bit lines in a planar layout, each for transmitting a column select signal;
• a plurality of bit line drive circuits arranged on opposite sides of the respective bit lines, each for supplying a write current for writing data into a memory cell to a corresponding bit line when being active;
• a plurality of bit line drive control circuits arranged corresponding to the bit line drive circuits, respectively, each bit line drive control circuit activating, in data writing, a corresponding bit line drive circuit in accordance with a write timing signal produced based on write data and a column select timing signal produced based on a column select signal on a corresponding column select signal, said column select signal being activated at a timing faster than the activation of said write timing signal and being deactivated at a timing later than deactivation of said write timing signal, and an active period of said write timing signal determining a time period of flow of the write current through the corresponding bit line;
• and
• digit line drive circuits arranged corresponding to said plurality of digit lines, for supplying a current to the digit line in a selected row according to an address signal in the data writing, a selected digit line drive circuit for the selected row being activated at a timing between activation of said column select signal and activation of said write timing signal, and being deactivated at a timing between deactivation of said column select signal and deactivation of said write timing signal.

A magnetic memory device comprising:

• a plurality of magnetic memory cells arranged in rows and columns;
• a plurality of write current lines arranged corresponding to the memory cell columns;
• a plurality of control signal lines of a divided structure arranged parallel to and non-overlapping in a planar view with the write current lines, in an interconnection layer different from a layer for said write current lines in an elevation view, each control signal line having divided interconnection-lines transferring a common control signal;
• and
• a plurality of current drive circuits arranged corresponding to the write current lines, each for supplying a write currents for writing data into the memory cell to a corresponding write current line according to the signal on a corresponding control signal line and write data when being active.