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US 2005/0231990 A1Published application
Semiconductor device
AssigneeRenesas Technology Corp.
InventorsTomoaki Uno, Masaki Shiraishi, Nobuyoshi Matsuura, Toshio Nagasawa
Life of this patent
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Abstract
A non-insulated DC-DC converter a power MOS·FRT for a highside switch and a power MOS·FET for a lowside switch. In the non-insulated DC-DC converter, the power MOS·FET for the highside switch and the power MOS·FET for the lowside switch, driver circuits that control operations of these elements, respectively, and a Schottky barrier diode connected in parallel with the power MOS·FET for the lowside switch are respectively formed in four different semiconductor chips. These four semiconductor chips are housed in one package. The semiconductor chips are mounted over the same die pad. The semiconductor chips are disposed so as to approach each other.
Claims28
A semiconductor device comprising:
- a first chip mounting section, a second chip mounting section and a third chip mounting section respectively disposed at intervals;
- a plurality of external terminals disposed around the first, second and third chip mounting sections;
- a first semiconductor chip disposed over the first chip mounting section and having a first field effect transistor;
- a second semiconductor chip disposed over the second chip mounting section and having a second field effect transistor;
- a third semiconductor chip disposed over the third chip mounting section and including a control circuit which controls operations of the first and second field effect transistors;
- a fourth semiconductor chip disposed over the second chip mounting section and having a first Schottky barrier diode;
- and
- a sealing body which seals the first, second, third and fourth semiconductor chips, the first, second and third chip mounting sections and some of the plurality of external terminals,
- wherein the plurality of external terminals include a first power supply terminal which supplies an input power supply potential, second power supply terminals which supply a potential lower than the input power supply potential, a signal terminal which controls the control circuit of the third semiconductor chip, and an output terminal which outputs an output power supply potential to the outside,
- wherein the first field effect transistor has a source-drain path series-connected between the first power supply terminal and the output terminal;
- wherein the second field effect transistor has a source-drain path series-connected between the output terminal and the second power supply terminal,
- wherein the control circuit of the third semiconductor chip controls respective operations of the first and second field effect transistors in accordance with a control signal inputted to the signal terminal,
- wherein the third semiconductor chip is disposed in such a manner that a distance between the third semiconductor chip and the first semiconductor chip is set shorter than a distance between the third semiconductor chip and the second semiconductor chip, and
- wherein the first Schottky barrier diode of the fourth semiconductor chip has a cathode electrically connected to the output terminal and an anode electrically connected to the second power supply terminal, and is electrically connected so as to be parallel with the second field effect transistor.
11 more elements
A semiconductor device comprising:
- a first chip mounting section, a second chip mounting section and a third chip mounting section respectively disposed at intervals;
- a plurality of external terminals disposed around the first, second and third chip mounting sections;
- a first semiconductor chip disposed over the first chip mounting section and having a first field effect transistor;
- a second semiconductor chip disposed over the second chip mounting section and having a second field effect transistor;
- a third semiconductor chip disposed over the third chip mounting section and including a control circuit which controls operations of the first and second field effect transistors;
- a fourth semiconductor chip disposed over the second chip mounting section and having a first Schottky barrier diode;
- and
- a sealing body which seals the first, second, third and fourth semiconductor chips, the first, second and third chip mounting sections and some of the plurality of external terminals,
- wherein the plurality of external terminals include a first power supply terminal which supplies an input power supply potential, second power supply terminals which supply a potential lower than the input power supply potential, a signal terminal which controls the control circuit of the third semiconductor chip, and an output terminal which outputs an output power supply potential to the outside,
- wherein the first field effect transistor has a source-drain path series-connected between the first power supply terminal and the output terminal;
- wherein the second field effect transistor has a source-drain path series-connected between the output terminal and the second power supply terminal,
- wherein the control circuit of the third semiconductor chip controls respective gates of the first and second field effect transistors in accordance with a control signal inputted to the signal terminal,
- wherein the second semiconductor chip is placed in a position closer to the second power supply terminal than the output terminal, and
- wherein the first Schottky barrier diode of the fourth semiconductor chip has a cathode electrically connected to the output terminal and an anode electrically connected to the second power supply terminal, and is electrically connected so as to be parallel with the second field effect transistor.
11 more elements
A semiconductor device according to claim 12, wherein the second power supply terminal to which the source of the second field effect transistor is electrically connected, and the second power supply terminal to which the anode of the first Schottky barrier diode is electrically connected, are separately formed and separated from each other.
A semiconductor device comprising:
- a first chip mounting section, a second chip mounting section and a third chip mounting section respectively disposed at intervals;
- a plurality of external terminals disposed around the first, second and third chip mounting sections;
- a first semiconductor chip disposed over the first chip mounting section and having a first field effect transistor;
- a second semiconductor chip disposed over the second chip mounting section and having a second field effect transistor;
- a third semiconductor chip disposed over the third chip mounting section and including a control circuit which controls operations of the first and second field effect transistors;
- a fourth semiconductor chip disposed over the second chip mounting section and having a first Schottky barrier diode;
- and
- a sealing body which seals the first, second, third and fourth semiconductor chips, the first, second and third chip mounting sections and some of the plurality of external terminals,
- wherein the plurality of external terminals include a first power supply terminal which supplies an input power supply potential, second power supply terminals which supply a potential lower than the input power supply potential, a signal terminal which controls the control circuit of the third semiconductor chip, and an output terminal which outputs an output power supply potential to the outside,
- wherein the first field effect transistor has a source-drain path series-connected between the first power supply terminal and the output terminal;
- wherein the second field effect transistor has a source-drain path series-connected between the output terminal and the second power supply terminal,
- wherein the control circuit of the third semiconductor chip controls respective gates of the first and second field effect transistors in accordance with a control signal inputted to the signal terminal,
- wherein the first semiconductor chip is disposed in such a manner that one side thereof approaches one side of the first chip mounting section, which is adjacent to one side of the second chip mounting section, and
- wherein the first Schottky barrier diode of the fourth semiconductor chip has a cathode electrically connected to the output terminal and an anode electrically connected to the second power supply terminal, and is electrically connected so as to be parallel with the second field effect transistor.
11 more elements
A semiconductor device comprising:
- a first power supply terminal for supply of a first potential;
- at least one second power supply terminal for supply of a second potential lower than the first potential;
- first and second field effect transistors series-connected between the first and second power supply terminals;
- first and second control circuits which are respectively electrically connected to inputs of the first and second field effect transistors and control operations of the first and second field effect transistors;
- and
- an output wiring section connected to a wiring that connects the first and second field effect transistors,
- wherein a cathode of a Schottky barrier diode is electrically connected to a wiring that connects an output of the first control circuit and the input of the first field effect transistor, an anode of the Schottky barrier diode is electrically connected to the second power terminal, and the Schottky barrier diode is electrically connected between a wiring that connects the output of the first control circuit and the input of the first field effect transistor, and the second power supply terminal.
4 more elements
Dependencies are inferred from the claim text.