Operational amplifier

An operational amplifier comprising:

• a first differential input portion including a first differential pair of MOS transistors for inputting a differential signal respectively and a first current source for supplying a constant current to said first differential pair of the MOS transistors, each of said MOS transistors having a well terminal;
• a second differential input portion including a second differential pair of MOS transistors for inputting said differential signal and a second current source for supplying a constant current to said second differential pair of MOS transistors, the polarity of said second differential pair of MOS transistors being opposite to the polarity of said first differential pair of MOS transistors;
• a summing portion for summing a current from said first differential input portion and said a current from said second differential input portion;
• and
• a well voltage control portion for controlling the well voltage of said first differential pair of the MOS transistors to keep being constant a source voltages of said first differential pair of MOS transistors, said well voltage control portion supplying each of the well terminal with an output signal generated in accordance with comparison result compared the source voltage of said differential pair of the MOS transistors with a predetermined reference voltage.

An operational amplifier comprising:

• a first differential input portion including a first differential pair of MOS transistors for inputting a differential signal respectively and a first current source for supplying a constant current to said first differential pair of the MOS transistors, each of said first differential pair of MOS transistors having a well terminal,
• a second differential input portion including a second differential pair of MOS transistors for inputting said differential signal and a second current source for supplying a constant current to said second differential pair of MOS transistors, the polarity of said second differential pair of MOS transistors being opposite to the polarity of said first differential pair of MOS transistors, each of said second differential pair of MOS transistors having a well terminal;
• a summing portion for summing a current from said first differential input portion and said a current from said second differential input portion;
• a first well voltage control portion for controlling the well voltage of said first differential pair of the MOS transistors to keep being constant a source voltages of said first differential pair of MOS transistors, said well voltage control portion supplying each of the well terminal of said first differential pair of the MOS transistors with an output signal generated in accordance with comparison result compared the source voltage of said first differential pair of the MOS transistors with a predetermined first reference voltage;
• and
• a second well voltage control portion for controlling the well voltage of said second differential pair of the MOS transistors to keep being constant a source voltages of said second differential pair of MOS transistors, said well voltage control portion supplying each of the well terminal of said second differential pair of the MOS transistors with an output signal generated in accordance with comparison result compared the source voltage of said second differential pair of the MOS transistors with a predetermined second reference voltage.

An operational amplifier comprising:

• a differential input portion including a differential pair of MOS transistors for inputting a differential signal respectively and a current source for supplying a constant current to said MOS transistors, each of said MOS transistors having a well terminal,
• a first cascode current source portion including a MOS transistor pair constituting a folded cascode circuit with said differential pair of MOS transistors, a first current source, and a second current source supplying a constant current to said MOS transistor pair respectively;
• a second cascode current source portion including a third current source and a fourth current source supplying a constant current to the MOS transistor pair of the first cascode current source portion respectively;
• and
• a well voltage control portion for controlling the well voltage of said differential pair of the MOS transistors to keep being constant a source voltages of said differential pair of MOS transistors, said well voltage control portion supplying each of the well terminal with an output signal generated in accordance with comparison result compared the source voltage of said differential pair of the MOS transistors with a predetermined reference voltage.

An operational amplifier comprising:

• a first differential input portion including a first differential pair of MOS transistors for inputting a differential signal respectively and a current source for supplying a constant current to said MOS transistors, each of said MOS transistors having a well terminal,
• a second differential input portion including a second differential pair of MOS transistors for inputting said differential signal and a second current source for supplying a constant current to said second differential pair of MOS transistors, the polarity of said second differential pair of MOS transistors being opposite to the polarity of said first differential pair of MOS transistors,
• a summing portion including a first MOS transistor pair constituting a first folded cascode circuit with said first differential pair of MOS transistors, a third current source and a fourth current source supplying a constant current to said first MOS transistor pair respectively, a second MOS transistor pair constituting a second folded cascode circuit with said second differential pair of MOS transistors, and a fifth current source and a sixth current source supplying a constant current to said second MOS transistor pair respectively, in which the first MOS transistor pair constituting the first cascode circuit and the second MOS transistor pair constituting the second cascode circuit are connected in series;
• and
• a well voltage control portion for controlling the well voltage of said first differential pair of the MOS transistors to keep being constant a source voltages of said first differential pair of MOS transistors, said well voltage control portion supplying each of the well terminal with an output signal generated in accordance with comparison result compared the source voltage of said differential pair of the MOS transistors with a predetermined reference voltage.

An operational amplifier comprising:

• a first differential input portion including a first differential pair of MOS transistors for inputting a differential signal respectively and a first current source for supplying a constant current to said first differential pair of MOS transistors, each of said first differential pair of MOS transistors having a well terminal,
• a second differential input portion including a second differential pair of MOS transistors for inputting said differential signal and a second current source for supplying a constant current to said second differential pair of MOS transistors, the polarity of said second differential pair of MOS transistors being opposite to the polarity of said first differential pair of MOS transistors, each of said second differential pair of MOS transistors having a well terminal;
• a summing portion including a first MOS transistor pair constituting a first folded cascode circuit with said first differential pair of MOS transistors, a third current source and a fourth current source supplying a constant current to said first MOS transistor pair respectively, a second MOS transistor pair constituting a second folded cascode circuit with said second differential pair of MOS transistors, and a fifth current source and a sixth current source supplying a constant current to said second MOS transistor pair respectively, in which the first MOS transistor pair constituting the first cascode circuit and the second MOS transistor pair constituting the second cascode circuit are connected in series;
• a first well voltage control portion for controlling the well voltage of said first differential pair of the MOS transistors to keep being constant a source voltages of said first differential pair of MOS transistors, said well voltage control portion supplying each of the well terminal of said first differential pair of the MOS transistors with an output signal generated in accordance with comparison result compared the source voltage of said first differential pair of the MOS transistors with a predetermined first reference voltage;
• and
• a second well voltage control portion for controlling the well voltage of said second differential pair of the MOS transistors to keep being constant a source voltages of said second differential pair of MOS transistors, said well voltage control portion supplying each of the well terminal of said second differential pair of the MOS transistors with an output signal generated in accordance with comparison result compared the source voltage of said second differential pair of the MOS transistors with a predetermined second reference voltage.